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Platform/Chip Abstraction Layer for multiple STM32 lines?

apullin
Associate II

Hi everybody,

Is there a commonly used or already-built system for platform/chip abstraction between multiple STM32 parts? I have encountered various PAL's over time, some better than others, but I was curious if there is one common one that people use when doing their own designs, and not already using a PAL baked into some vendor's SDK?

I am about to set out work on a new module in a hardware system that has two possible paths in front of it, one blank-page and one backwards compatible.
Roughly speaking, I might be extending a module already designed with an STM32F2 or the module might throw off it's legacy needs and then we could build it with an STM32U5. Or there's even a third avenue wherein we'd update the legacy section of the system and target STM32U5 hardware.

I can generate the template code for the F2 and U5, and then include both in a larger project.
Conceptually, I can see how e.g. CAN functions would just need to be routed to each library's CAN implementations, and it's probably even the case that the STM32 HAL has identical semantics for both.

And conceptually I can see how generic resources like timebases and pulse generators could be written with a layer that would then just need to be shimmed to each chip's specifics, and a choice of actual silicon peripheral, e.g. LPTIMx vs TIMx, etc.

But ... will I need to invent all of that myself from scratch? Has someone already done it in a way that I can just borrow?
Any recommendations would be appreciated!
(yes, doing it all myself from scratch would be a good skill builder, but, well, my time in limited)

I have looked at the Zephy project. They seem to have a fairly complete system for this ... but all as part of their build and config system. In this case, I am constrained to using ThreadX (or ... ugh ... Green Hills), so trying to excise and re-use their PAL might be too big a task.

2 REPLIES 2
TDK
Guru

The HAL (Hardware Abstraction Library) library does exactly this.

Things can't be exactly the same across multiple lines because the peripherals and functionality change between lines, but it's probably as close as you can get without constraining yourself to a limited subset of available features.

If you feel a post has answered your question, please click "Accept as Solution".

No, the HAL does not fit the described need. The HAL abstracts away the actual register-level implementations.

I was asking about something that operates at a level above that - which would be a routing or shim layer between an even more abstract representation of resources. Even if is just a bunch of stubs I then have to decide how to connect to the F2 and U5 HALs, without necessarily having to custom engineer the whole framework.