DMA/STM32F103: memory to USART2 TX.

[LarryC]

Hi all, I am successfully transferring from a memory location to the data register of USART2 Tx using DMA operation. And the USART2 has been used by the  printf()  to output to the PC. 

What I don't understand is, what moderates the rate at which DMA moves data from memory location to the Tx data register? Obviously, data cannot be moved to Tx data register faster than it can transmit, otherwise there would be overwrite errors. Nor should the data be moved at a much slower speed than the Tx can handle, otherwise time would be wasted.

So what is the mechanism that moves the data to Tx data register at just the right rate?  I did not set any Tx transmit complete flags or ISRs to indicate to the DMA the completion of the last transmission out of the Tx data register.    Thanks in advance for your help and explanation!

[Pavel A. · Accepted solution]

DMA is connected to the UARTs and other things that work with DMA, via special lines called DMA requests. These lines signal when it's time to move the next data portion.

[LarryC]

Hi Pavel , ok so DMA activities are automatically synchronized as far as what I concerned about.  It makes sense because the programmers should not have to be involved with the internal workings at that level, which would have been meaningless as far as the project is concerned. But it means we can be assured that there is a mechanism that manages just that behind the scenes. I will be more than happy to accept it as a functioning block/module/black box.  Thank you for the input!

[Tesla DeLorean]

It's demand paced by TXE, ie the time immediately after the content of the TDR is moved to the output shift register you can't see. So there's about a byte-time for it to service, to account for any latency or contention, that's apt to be orders of magnitude, or more, faster than the baud clock shifting bits out.