I've got a program running on a dual-core STM32 (the STM32H747IGT6 if you're curious) and right now it's doing a pile of SCB_CleanDCache_by_Addr() and SCB_InvalidateDCache_by_Addr() to keep shared memory in sync between the CM4 and CM7. I was thinking it would be easier if I just set the shared area to non-cacheable, but when I configure the MPU the system will work for a few seconds and then hang.
The shared memory area is called 'buffer_control' and I padded it to 512 bytes. My MPU configuration looks like this:
SCB_EnableDCache();
SCB_EnableICache();
/* Disable the MPU */
__DMB(); /* Make sure outstanding transfers are done */
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; /* Disable fault exceptions */
MPU->CTRL = 0; /* Disable the MPU and clear the control register*/
/* Configure the MPU attributes as WB-WA for SRAM */
MPU->RNR = MPU_REGION_NUMBER0;
MPU->RBAR = (uint32_t)&buffer_control;
MPU->RASR = ((uint32_t)MPU_INSTRUCTION_ACCESS_DISABLE << MPU_RASR_XN_Pos) |
((uint32_t)MPU_REGION_FULL_ACCESS << MPU_RASR_AP_Pos) |
((uint32_t)MPU_TEX_LEVEL0 << MPU_RASR_TEX_Pos) |
((uint32_t)MPU_ACCESS_SHAREABLE << MPU_RASR_S_Pos) |
((uint32_t)MPU_ACCESS_NOT_CACHEABLE << MPU_RASR_C_Pos) |
// ((uint32_t)MPU_ACCESS_NOT_BUFFERABLE << MPU_RASR_B_Pos) |
// ((uint32_t)MPU_InitStruct.SubRegionDisable << MPU_RASR_SRD_Pos) |
((uint32_t)MPU_REGION_SIZE_512B << MPU_RASR_SIZE_Pos) |
((uint32_t)MPU_REGION_ENABLE << MPU_RASR_ENABLE_Pos);
/* Enable the MPU */
MPU->CTRL = MPU_PRIVILEGED_DEFAULT | MPU_CTRL_ENABLE_Msk; /* Enable the MPU */
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; /* Enable fault exceptions */
__DSB(); /* Ensure MPU setting take effects */
__ISB();
What am I doing wrong?
p.s. buffer_control is located at the start of SRAM2 with the address 0x30020000
