Hi all,
I have the following problem: the backup domain registers are sometimes cleared on power off/on, despite having a 3V coin cell CR1632 connected to the pin VBAT and the GND plane. The RTC registers are then cleared.
The error occurs sporadic. Typically between 1 to 20 times of disconnecting/connecting the VDD supply.
Due to the missing power, I cannot debug while the bug appears.
The code was not generated using Cube or HAL libraries.
The uC used is an STM32F207IGT6 mounted on a proprietary PCB.
I already checked/tried the following:
- Setting the BDRST bit in the RCC_BDCR register would cause a software reset of the Backup Domain. This bit is never set to 1 by the software (as far as I can tell)
- There is a 100nF ceramic capacitor across the battery, stabilizing the voltage. The voltage seems stable, no drop or spike during turn off/turn on of VDD (measured across this 100nF capacitor).
- Everything else works fine on the microcontroller; the RTC registers seem to be fine, I can read back the correct time and data except the the bug occurs. From that point, the time and data start counting from zero upwards...
Here is the body of the RTC function:
/******************************************************************************************************************************/
/** @brief This function enables the RTC peripheral in the firmware (LSE clock). Furthermore it checks whether the daylight save
* time should be active or not.
* @param none
* @return none
*/
/******************************************************************************************************************************/
void startRTC(void) {
RCC->APB1ENR |= RCC_APB1ENR_PWREN; // enable clock for Power interface (Other notation: APB1ENR = APB1ENR | 0x10000000, RCC_APB1ENR 0x4002384)
PWR->CR |= PWR_CR_DBP; // enable access to RTC, BDC registers
while ((PWR->CR & PWR_CR_DBP) == 0); // wait for DBP = 1 (due to errata sheet)
RCC->BDCR |= RCC_BDCR_LSEON; // enable LSE
while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0); // Wait for LSERDY = 1 (LSE is ready)
RCC->BDCR |= (RCC_BDCR_RTCSEL_0 | RCC_BDCR_RTCEN); // set RTC clock source, enable RTC clock
PWR->CR &= ~PWR_CR_DBP; // disable access to RTC registers
while ((PWR->CR & PWR_CR_DBP) != 0); // wait for DBP = 0 (due to errata sheet)
checkAndSetDST();
}
Has anyone had a similar problem? If yes, what was the solution?
Thanks a lot for your help,
Clara
