PCB: How to wire two SDRAM ICs to STM32F7?

[Lars Beiderbecke]

Hello,

The STM32F7 supports up to two external SDRAM ICs, where both SDRAM ICs basically share the same set of pins. Given all the restrictions on creating traces between STM32 and SDRAM (different layers, same length, same number of vias, ...), how can I possibly wire two ICs to the same STM32?

Do I need to double the number of layers? Can I create a split (junction) in every trace?

What is the best strategy for this? Are there any successful examples?

[Peter BENSCH]

If you want to work with two external SDRAM, not only the address and data lines have to be wired in parallel, i.e. to both SDRAM, but also the signals Clock Enable (SDCKE) and Chip Enable (SDNE). With the latter, the FMC can access the individual SDRAMs.

The mode of operation is explained in the respective reference manual, e.g. in the SDRAM controller section, or in a training course under section Flexible Static Memory Controller (FSMC).

Regards

/Peter

[Lars Beiderbecke]

Thanks, Peter, for your response. This part has been clear to me.

But how would a PCB layout have to look like? You say I should wire lines in parallel. Does that mean that for each signal, I should have two traces that are joined right at the STM32? Or can that join be somewhere else, e.g., midway between the STM32 and SDRAM IC #1? Does the join have to be at the same point for every signal, or can it vary?

I've been following application note AN4661 to create my PCB with a single SDRAM IC. The trace routing seems to be very sensitive to deviations from that reference design, hence this post.

An example layout would be very helpful. I've checked ST's dev boards, but none have two SDRAM ICs.

[Peter BENSCH · Accepted solution]

Well, there are reasons for using as little external RAM as possible:

• price of board, layout and additional components,
• bus load,
• access speed (throughput),
• long-term availability?,
• etc.

Already because of the bus load (load impedance vs. driver), the number of DRAMs that can be connected in parallel to an address bus is limited. One should therefore carefully check whether the FSMC/FMC can drive the total impedance of the connected DRAMs.

Parallel connection means here that the address bus from the STM32 is first routed to SDRAM 1 and from there to SDRAM 2, similar to SDRAM modules known from desktop computers.

Good luck!

/Peter

[Lars Beiderbecke]

I see, thanks for the explanation!

The better solution, of course, would be if the STM32F7s would support DDR RAM. 😉