ST25DV wear leveling, what is the default cleared state of user memory byte

[notram]

Hi all!

I'm trying to implement a wear leveling in user memory accessed from I2C for a counter on bit level. My question is:

Are ST25DV eeprom byte cells similar to classic ones where each write cycle starts with a clear (which sets the byte to 0xFF) and after it writes 0 bits where needed? Or is there somewhere an inversion taking place? Could someone help me, by pointing out some directions in datasheets for me in this matter?

I found another post where memory default state is quoted from the datasheet which specifies that factory default is 0x00, but this doesn't imply that it's default state isn't 0xFF.

Thanks in advance, 

notram

[JL. Lebon]

Hello, 

In the ST25DV, the EEPROM erase state is 0x00 for each byte.
A write cycle starts with an erase of the byte, which sets the byte to 0x00, and then only 1 bits are written where needed.

For wear leveling, you can consult the AN5085 application note about on cycling. It may answer some of your questions (Cycling endurance and data retention of EEPROMs in products of the ST25DV-I2C series, based on the CMOS F8H process - Application note).

Best regards.