How to Modify RFAL Library for ST25R3918 Without ST25R3916_CMD_TEST_ACCESS Register

zeynepdicle · ‎2023-09-28

I am using the ST25R3918 and the 'pollingTagDetect' example from the RFAL library. This chip does not have the ST25R3916_CMD_TEST_ACCESS register.

How can I modify this library?

zeynepdicle · ‎2023-10-05

Hi,

I hope understood correctly.

Rgds

ZD

Brian TIDAL · ‎2023-10-05

Hi,

the SPI clock seems to be around 40kHz (if I am not wrong, this is usually 5MHz in our demos). Do you confirm? The reading of the interrupt status takes 1.5ms to be compared with the 2ms margin for the General Purpose Timer expiry in the SELFTEST_TIMER. Any reason to have such a low speed on the SPI? What is your MCU clock configuration? Make sure to have the proper SPI prescaler in order to reach ~4 MHz or increase the margin in the SELFTEST_TIMER or disable the SELFTEST_TIMER.

Rgds

BT

In order to give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

zeynepdicle · ‎2023-10-06

Hi,

I use these values. I tried many options and this is the best result.
If I use the high speed value, I cannot see SPI communication in Logic Analyzer.

Rgds

ZD

Brian TIDAL · ‎2023-10-06

Hi,

"If I use the high speed value, I cannot see SPI communication in Logic Analyzer." Well, make sure to properly configure your Salae device (go to device settings and configure the proper sampling rate in order to be able to capture SPI at 4MHz i.e. > 20 M sample per second)

A 62.5 kHz clock for the SPI causes transfer duration that is not really compatible with a 2 ms margin to check the accuracy of the systick in the SELFTEST_TIMER... Again I would recommend to use 4MHz (prescaler 4 for a SYSCLK of 16MHz).

Rgds

BT

In order to give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

zeynepdicle · ‎2023-10-06

Hi,

OK I am going to try.
I use ST25R3918 and my colleagues designed it. When I check the PCB. I saw that the schematic was correct but the layout was not correct as per the layout recommendations.
Could there be a problem with this situation?

Rgbs
ZD

Brian TIDAL · ‎2023-10-06

Hi,

I can hardly comment. At least, let test SPI communication at 4MHz on this board.

Rgds

BT

In order to give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

zeynepdicle · ‎2023-10-06

Hi

Ok, I changed SYSCLICK 16 MHz, HCLK 16 MHz and Prescaler (for Baud Rate) 4.
The same error continues.

Brian TIDAL · ‎2023-10-06

Hi,

inside the SYSTICK interrupt handler, toggle a GPIO and trace this GPIO in Salae in addition to the SPI+IRQ. Then send me the salae file (I can hardly investigate on screenshot...).

Rgds

BT

In order to give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

zeynepdicle · ‎2023-10-08

Hi,

You can access the file from this link.

Rgds

ZD

Brian TIDAL · ‎2023-10-09

Hi,

make sure to follow Salae recommendation regarding the sampling rate (https://support.saleae.com/faq/technical-faq/what-sample-rate-is-required). With a SPI clock at 4MHz, a 8MS/s sampling rate is not enough to provide a reliable trace: some SPI clock ticks are randomly lost as in the following screen shot

Can you confirm that ST25R3916_TEST_TMR_TOUT has not been modified (this is 20ms in the genuine code)?

Also can you confirm that a 27.12 MHz crystal is being used on your custom board?

Rgds

BT

In order to give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.