I am evaluating the VN9D5D20F 4-channel high-side driver for a design (https://www.st.com/en/automotive-analog-and-power/vn9d5d20f.html).
According to the datasheet, the PWM clock should be provided via the PWM_CLK input, but there's also this note about the PWM fallback clock:
"When PWMCLOCKLOW warning flag is set, an internal fallback clock (at a typical frequency of 400 kHz) is used
to substitute the external one."
My question is: can the fallback clock be used in place of providing a clock via the PWM_CLK input? Does the fallback clock get divided and the duty cycle/phase applied as if it were coming from the PWM_CLK input?
