SPI interface where slave returns a delayed clock for MISO

[Keerthi]

Hi,

I am using differential SPI communication with an STM32G474. The master sends the clock (SCLK) to the slave and data through the MOSI line. However, the slave responds on MOSI using a delayed clock (DCLK), which is derived from the master clock with some delay (DCLK = SCLK*Delay).

This means the master must read from the slave using DCLK instead of SCLK. I’m sure this cannot be handled through the normal SPI peripheral.

Could someone suggest a solution for this scenario?
One idea I had was:

1. Use another SPI peripheral on the STM32, configure it as a slave, and use the delayed clock (DCLK) from the slave device as the input clock to capture the return data.

Would this approach work, or is there a better method?

Thank you in advance

[AScha.3]

At 60Mbit is more a job for a fpga.

[Keerthi]

But I am planning to use the microcontroller instead of FPGA. Because even STM32G474 can provide maximum SPI frequency upto 75MHz. 

[Andrew Neil]

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@TDK wrote:

This is not differential signaling. Sounds much more like "delayed".

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Agreed.

Title edited to better describe the situation.