Posted on May 17, 2011 at 09:40If I don't set the WSR_AHB bit in SCR0, memory to memory DMA never finish! (it never starts)
WSR_AHB: AHB Wait state enable
This bit is set and cleared by software to enable/disable the insertion of a wait
state during an SRAM read access performed on the AHB bus
0: No wait state
1: 1 wait state (default)
Like the SRAM arbiter don't let the DMA to access the AHB!
Is this a normal behavior? I'm runing at 96 MHz.
What should I read to understand how these setting influence system performance? Less wait-states should be better ?
WSR_AHB,WSR_DTCM are set by default and usually startup files leave them in 1. It may because of this?
thanks,
Andras
