2008-01-20 10:39 PM
2011-05-17 12:49 AM
Hi, I'am sending data from emi port to a fpga, and it works!
I need to speeding up as well as possible writings to emi port. I notice first of all, that CS signal spent a lot of time to come back from logic level 0. Changing parameters of emi delay and wait states, seems to be very little think in order to the CS caming up delay! ... some suggestion? Thanks Luca