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BluePill: bidirectional SPI communication between STM32F103C and ESP8266

its-nott-me
Associate

Split from BluePill: bidirectional UART communication between STM32F103C and ESP8266 - this is a different topic (SPI instead of UART).


Extremely sorry for the late reply..

 

A master–slave SPI network connects one ESP8266 (master) to a chain of STM32F103C controllers (slaves).

Each STM32 drives a 28BYJ-48 stepper motor through a ULN2003 driver.

Communication is full-duplex SPI, where the ESP8266 sends movement or configuration commands and receives acknowledgment or state feedback from each STM32.

 

Communication Flow

ESP8266 polls each STM32 sequentially via Chip Select (CS) or multiplexed addressing.

Command frame (e.g., [Header][Target Steps][Checksum]) sent via MOSI.

STM processes command, actuates motor, then replies over MISO with [Status][Position][ErrorFlag].

Duplex SPI allows command–response in the same transaction.

Future scalability: plug-and-play detection using pre-assigned hardware IDs or serial enumeration through data lines.

 

Data Framing Example

Master → Slave:

[STX][CMD_ID][TARGET_POS][SPEED][CRC][ETX]

Slave → Master:

[STX][STATUS][CUR_POS][ERR][CRC][ETX]

 

Both directions are synchronized in a single SPI transaction for minimal latency.

 

Core Objective

Reliable duplex SPI communication between ESP8266 master and multiple STM32 slaves, allowing modular, plug-and-play addition of slave boards while maintaining synchronized control and feedback for each motor unit.

 

mermaid diagram:

https://www.mermaidchart.com/d/f91347c4-c7de-49ca-ba6c-be2851b868d7

EDIT - This is the diagram:

AndrewNeil_0-1763237720027.png

 

1 REPLY 1
Andrew Neil
Super User

Your protocol doesn't seem to have any way to address the STM32s ?

You are only applying clock to STM32 #1 - how do the others get clocked ?

As shown, the response from STM32 #1 would have to be clocked through #2 and #3 before it gets back to the ESP.

Similarly, a command for STM32 #3 would have to be clocked through #1 and #2.

Is this what you intend?

 


@its-nott-me wrote:

allowing modular, plug-and-play addition of slave boards


How will the master know how many slaves are in the chain?

 


@its-nott-me wrote:

Data Framing Example

Master → Slave:

[STX][CMD_ID][TARGET_POS][SPEED][CRC][ETX]

Slave → Master:

[STX][STATUS][CUR_POS][ERR][CRC][ETX]


The STX...ETX framing doesn't really make sense for SPI - I presume this is just a hangover from the UART version?

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