Posted on April 18, 2007 at 08:48To all gurus,
This can be seen here:
http://mcu.st.com/mcu/modules.php?mop=modload&name=Splatt_Forums&file=viewtopic&topic=5220&forum=17 Basically, I am using ST7 IAP for my firmware upgrading. I have modified the IAP to work with interrupt handled UART. The problem i am facing now is that I am not able to launch my user program now. I notive that the cause is by the enhanced interrupt controller init (EIC_INIT) in 75x_init.s. If I remove EIC_INIT, i am able to launch my user program successfully but now my interrupt ISR will not work. Is there a way to resolve this? Thanks
#ifdef EIC_INIT
LDR r3, =EIC_Base_addr
LDR r4, =0x00000000
STR r4, [r3, #ICR_off_addr] ; Disable FIQ and IRQ
STR r4, [r3, #IER_off_addr] ; Disable all interrupts channels
LDR r4, =0xFFFFFFFF
STR r4, [r3, #IPR_off_addr] ; Clear all IRQ pending bits
LDR r4, =0x18
STR r4, [r3, #FIR_off_addr] ; Disable FIQ channels and clear FIQ pending bits
LDR r4, =0x00000000
STR r4, [r3, #CIPR_off_addr] ; Reset the current priority register
LDR r4, =0xE59F0000 ; Write the LDR pc,pc,#offset..
STR r4, [r3, #IVR_off_addr] ; ..instruction code in IVR[31:16]
LDR r2,= 32 ; 32 Channel to initialize
LDR r0, =WAKUP_Addr ; Read the address of the IRQs address table
LDR r1, =0x00000FFF
AND r0,r0,r1
LDR r5,=SIR0_off_addr ; Read SIR0 address
SUB r4,r0,#8 ; subtract 8 for prefetch
LDR r1, =0xF7E8 ; add the offset to the 0x00 address..
; ..(IVR address + 7E8 = 0x00)
; 0xF7E8 used to complete the LDR pc,offset opcode
ADD r1,r4,r1 ; compute the jump offset
EIC_INI
MOV r4, r1, LSL #16 ; Left shift the result
STR r4, [r3, r5] ; Store the result in SIRx register
ADD r1, r1, #4 ; Next IRQ address
ADD r5, r5, #4 ; Next SIR
SUBS r2, r2, #1 ; Decrement the number of SIR registers to initialize
BNE EIC_INI ; If more then continue
#endif
