SDRAM controller info

davidc · ‎2003-06-05

Posted on June 05, 2003 at 12:40

davidc · ‎2003-05-28

Posted on May 28, 2003 at 16:26

Atlas SDRAM controller.

The programming manual 1ssue 1.0, page 100 says ''see chapter 6.3 ''clock considerations''.

Sadly 6.3 is not that, and I can't find the words ''clock considerations'' anywhere in the document......

Anyone any idea if this info exists anywhere?

I'd like to find out exactly how the numbers in the MEM_REGn registers relate to actual timing, especially the RCDP field which seems to be completely undocumented.

stephen239955_st · ‎2003-06-04

Posted on June 05, 2003 at 07:34

The clock consideration you mention are actually related to the datasheet and not the programming manual.

With reference to RCDP, these bits should be set to 0000. In fact, they should not be documented in this manner. Setting these bit to any other value may cause unstable behaviour of the STPC.

davidc · ‎2003-06-05

Posted on June 05, 2003 at 12:40

Thanks. I'll take reference to RCDP as a documentation error then. But there remain a number of other bits in these registers, LHDI and friends for a start, whose meanings ( and usage ) are left to the imagination.

Has anyone written anything fuller on how these registers should be set, and under what circumstances?