BSPI and Fifos

tech9 · ‎2006-07-03

Posted on July 04, 2006 at 06:25

BSPI and Fifos

tech9 · ‎2006-06-20

Posted on June 20, 2006 at 12:57

Hello all,

We are currently using the BSPI0 on a STR71, with the fifos on.

The depth is 7 words deep.

The receive interrupt is configured to trigger when the receive fifo is full.

However, it is set when we get only 1 word in it; it seems that both flags are set together (RFNE and RFF, respectively receive fifo not empty and receive fifo full).

Is there something undocumented about those flags?

Additionnally; where are those fifos mapped in memory? Are we only able to see the first word in the BPSI registers?

Thanks for any input!

Tech

stankovic · ‎2006-07-03

Posted on July 04, 2006 at 06:25

Hi,

I didn't have a time to check STR71x (I am working with STR73x) but as it is same family this should be same.

FIFO is actualy on same address - all 16 of them.

So for reading data from FIFO you can do something like this:

for(i=0; iRXR); }

You are practticaly reading same addres 7 times but every time receiving new byte.

It is same procedure for writing in - you write byte after byte on same address.

I hope this will help.