Posted on November 23, 2016 at 11:18Hello Aurelien ,
Here is the feedback of a SPC5x Expert,
''First of all, the documentation about hardware interrupts is unclear and could confuse the reader
With an unclear documentation I did a simple test by enabling hardware interrupts (HVEN = 1)
and using PIT0 as source of interrupt.
As soon as a PIT0 interrupt is fired the Program Counter (PC) is set to 0x000018EC where:
- 0x8EC is the PIT0 offset
- 0x1000 is the vector table offset
In order to manage the (hardware) interrupt in hardware mode, at address 0x000018EC need to have a branch ('bl') instruction
which redirect the execution flow to the user interrupt handler.
The user interrupt handles will be responsible to acknowledge the interrupt source and to return to normal
execution (using an ‘rfi’ instruction at the end).
For each hardware interrupt, in the hardware vector table, 4 bytes available (see table 155 in Reference manual)
At the end, the vector table should be a list of branch instructions and the vector table must be
placed (by a linker script directive) to a specific address (0x00001000 in case of Bolero)''
Best regards
Erwan
