2019-04-24 09:01 AM
P4SEL |= 0x06; // Assign I2C pins P4.1, P4.2 to USCI_B1
UCB1CTL1 |= UCSWRST; // Enable SW reset
UCB1CTL0 = UCMST + UCMODE_3 + UCSYNC; // I2C Master, synchronous mode
UCB1CTL1 = UCSSEL_2 + UCSWRST; // Use SMCLK
UCB1BR0 = 12; // fSCL = SMCLK/12 = ~100kHz
UCB1BR1 = 0;
UCB1CTL1 &= ~UCSWRST; // Clear SW reset, resume operation
ret = lsm303agr_read_reg(ctx, LSM303AGR_WHO_AM_I_A, &ACC_Data_Raw[0], 1);
How do I define ctx?
2019-05-13 08:55 AM
Hi jerry, if that code doesn't work (ctx should be the I2C slave ADDR that for lsm303agr is 0011001b on 7-bit), you could check with the code from here lsm303agr.c. In general, you can point our you findings directly on the STMems_Standard_C_drivers github forum. Regards