Dear SIR,
When FIFO mode is disable. And Polling mode is used.
There is a bit DRDY_MASK in registerCTRL4_C(0x13), 1 : mask DRDY on pin (both XL & Gyro) until filter settling ends (XL and Gyro independently masked).
It says that it mask DRDY on pin, it dos NOT raise interrupt INT1 or INT2 until filter setting ends.
When polling mode is used, does it means that it mask bit XLDA and GDA to b'0 when filter is not complete(data is not ready)in STATUS_REG?
Thanks,
E-John
