LSM6DSO High pass filter questions

[el659]

Hi, I need some clarification about digital high-pass filter in LSM6DSO since the datasheet and application note for LSM6DSO seem to lack explanation about certain features of it (or I just didn't get it).

1. In on page 20 of AN5192 (refer to the image below) showing a table of accelerometer bandwidth selection in mode 1/2/3, it has a list of max overall settling time (samples to be discarded). Does this max overall settling time referring to only the initial period of time when the HP_SLOPE_XL_EN bit is set to 1 and the accelerometer starts producing data or is it referring to the periods from time to time when there are abrupt changes in the accelerometer reading?

2. On the same page I mentioned in question 1, it briefly talks about fast settling mode but it doesn't really talk about how fast it shortens the settling time of the low-pass/high-pass filter of LSM6DSO. How fast does the fast-settling mode do the job for either filters? Is there any specific specification about it?

3. On the same page again, it says for fast-settling mode that, "The selected filter sets the second sample after writing this bit." I simply didn't understand what this sentence meant.

Thanks in advance,

[Federica Bossi]

Hi @el659 ,

1) The table refers to the initial period, however this is not the only case, it also applies when the filter band itself is changed by the HPCF_XL[2:0] bits. 

2) the step response time is always valid, both when the filter starts from an initialization state and when it sees an acceleration step at its input

3) It is the answer to question #2, the filter is set 2 samples later from the writing of the bit.