lsm6dsl to catch peak shock load

[Matti Sillanpaa]

Hi.

We are trying to configure lsm6dsl to catch peak shock. The usecase is that the sensor should sleep until shock occurs (say above 1g on any axis), cause interrupt and have the value available in FIFO. We are using the STMems_Standard_C_drivers from ST as base. We are using I2C for the communication.

My configuration:

 lsm6dsl_device_id_get(&dev_ctx, &whoamI);
 
 lsm6dsl_reset_set(&dev_ctx, PROPERTY_ENABLE);
 
 do {
 
   lsm6dsl_reset_get(&dev_ctx, &rst);
 
 } while (rst);
 
/*
 
  * Set Output Data Rate
 
  */
 
 lsm6dsl_xl_data_rate_set(&dev_ctx, LSM6DSL_XL_ODR_416Hz); //
 
 /*
 
  * Set full scale
 
  */ 
 
 lsm6dsl_xl_full_scale_set(&dev_ctx, LSM6DSL_4g);
 
 lsm6dsl_wkup_threshold_set(&dev_ctx, 4);
 
  routing2.int2_wu = 1;
 
  delay_ms(4); /* per ST AN5040*/
 
 
 lsm6dsl_pin_int2_route_set(&dev_ctx, routing2);
 
 
 lsm6dsl_fifo_xl_batch_set(&dev_ctx, 1);
 
 lsm6dsl_fifo_data_rate_set(&dev_ctx,LSM6DSL_FIFO_104Hz);
 
 lsm6dsl_fifo_mode_set(&dev_ctx, LSM6DSL_BYPASS_TO_STREAM_MODE);

Few registers:

INT2_CTRl: 0
md2: 20
PULSE_CFG_G: 0
TAP_CFG: 80
INT2_CTRl: 0
FIFO_CTRL3: 1
FIFO_CTRL5: 24
master config: 0
ctrl1: 68
ctrl2: 0
ctrl3: 4
ctrl4: 0
ctrl5: 0
ctrl6: 0
ctrl7: 0
ctrl8: 0
ctrl9: e0
ctrl10: 0

Problem is that the I would like to get fifo full interrup when the interrupt occurs. I normally get several interrupts per shock. The fifo isn't even nearly full (about 3-17 samples).

I tried then to route the fifo full interrupt to int1 (which I actually listen) and the shock to int2 (which is just trigger to start filling the FIFO)

 routing1.int1_full_flag = 1;
 
 lsm6dsl_pin_int1_route_set(&dev_ctx, routing1);

However this causes even more interrupts.

***********************************************************

I've been through the application note (AN5040), however it doesn't define usecase for maximum shock detection and especially configuring the fifo to get the value for it.

[Matti Sillanpaa]

Ok, no I think I have this working.

Apparently the fifo ODR speed had to be _less_ than the accelerometer ODR speed. Unlike in the application note where it's mentioned to be same or less.

[Miroslav BATEK]

The ODR_FIFO_[3:0] bits of FIFO_CTRL5 define the maximum data rate at which data are stored in FIFO. The FIFO ODR can be the same as the accelerometer ODR, it can be also higher.

I don;t think this is root cause of your problem.

[Matti Sillanpaa]

Would it be possible to get pseudo code walk through of the assumed configuration? I switched also to stream to fifo mode. It seems to have relatively valid data.

However I'm still a bit baffled about the configuration. Most accelerometers I've worked before have possibility to trigger the fifo _after_ it's been filled with predefined amount of samples from wakeup event for peak load detection.

[Matti Sillanpaa]

"Most accelerometers I've worked before have possibility to trigger the fifo _after_ it's been filled with predefined amount of samples from wakeup event for peak load detection."

What I mean to say with this gibberish, is that it's possible to get fifo full interrupt where fifo has been filled after trigger event (say peak load). With x amount of pre-trigger data and y amount of post trigger data.