Case Description:
Title: LSM6DSL FIFO data misalignment (XYZ rotated) and FIFO_PATTERN always 0 — how to align reads?
Body:
I’m using an LSM6DSL over I²C with an STM32. Goal: batch accelerometer-only samples into FIFO and drain clean (x,y,z) triplets at a fixed watermark. I keep running into two issues:
- Data misalignment — the XYZ triplets appear “rotated”. I’ll get a few normal lines, then a line where one column looks like a big random number (e.g., ~168xx), then it stabilizes again. Example:
x,y,z
5, 250, 16870,
17, 258, 16825,
-66, 221, 16828,
-53, 284, 16834,
Sampling End
Sampling Start
-22, 4, 242,
16846, 13, 281
16830, 51, 230
16882, 39, 242
16850, 11, 258
16803, -14, 220
16843, -24, 232
16855, 0, 241
- FIFO_PATTERN is always 0 — I expected to use FIFO_STATUS3/4 (FIFO_PATTERN[9:0]) to know which axis comes next and align before parsing, but I always read 0, even when the FIFO is clearly non-empty and STOP_ON_FTH has fired.
Hardware
- LSM6DSL @ 3.3V, I²C 400 kHz
- SDO tied low → 7-bit addr 0x6A
- MCU: STM32 (HAL I²C)
Config summary (accelerometer-only)
- CTRL1_XL: ODR = 833 Hz, FS = ±2g, high-perf
- CTRL2_G: 0 (gyro off)
- CTRL3_C: BDU=1, IF_INC=1, BLE=0 (little-endian)
- FIFO_CTRL1/2: watermark = 1536 words (for 512samples × 3 words/sample)
- FIFO_CTRL3: BDR_XL = NO_DEC, BDR_GY = DISABLE
- FIFO_CTRL4: STOP_ON_FTH = 1, ONLY_HIGH_DATA = 0
- FIFO_CTRL5: ODR_FIFO = 833Hz, FIFO_MODE = STREAM
- TIMER_PEDO_FIFO_EN=0, FIFO_TEMP_EN=0 (don’t want timestamp or temp in FIFO)
Sanity checks:
- WHOAMI is correct, soft reset works.
- DIFF_FIFO reports levels that match watermark (in words).
- Endianness is little; parsing uses int16_t from LSB/MSB correctly.
- Reading from FIFO_DATA_OUT_L with auto-increment.
What I tried
- Reading FIFO_PATTERN (STATUS3/4) right before burst read. It always returns 0, so pattern % 3 == 0 and my code assumes next word is X, but the log suggests I’m sometimes starting at Y or Z.
- Toggling STOP_ON_FTH on/off and changing ODRs.
- Ensuring temp/timestamp/DS3/DS4 are disabled so only accel data is batched.
- Full device reset between runs.
