LIS2DW12 - Requirement of latching for inactivity/activity and FIFO mode of bypass-continuous

[ZAIDS-S23]

Greetings

I am trying to utilise the FIFO of the LIS2DW12, in bypass-continuous mode, which requires the latched-interrupt bit (LIR) in CTRL3 register to be set, as stated in the application note AN5038.

In the ISR for the FIFO_FTH, I am reading the output registers, resetting the fifo by putting it into bypass mode, then putting it into bypass-continuous mode. The interrupt to trigger the chip is a wake-up event.

I want to also utilise the inactivity/activity functionality of the accelerometer, allowing it to save power. This requires the LIR bit of CTRL3 register to be in a reset state. 

How does one propose I work around the contradiction of either setting the LIR bit or not?

@Federica Bossi

[Federica Bossi]

Hi @ZAIDS-S23 ,

I think you are referring at this statement in the Application Note: 

During the inactivity status of the device, the SLEEP_STATE bit in STATUS is set high. This bit can be routed to the INT2 pin, setting both the INT2_SLEEP_STATE and INT2_SLEEP_STATE_CHG bits to 1 in CTRL5_INT2_PAD_CTRL. Note that this signal is not compatible with "latched notification mode", the LIR bit of CTRL3 should be set to 0.

Is it right?

If yes, this limitation refers only to INT2_SLEEP_STATE, and not only to INT2_SLEEP_STATE_CHG as described in the next sentence:

Every time the device status changes from activity to inactivity or vice versa, the SLEEP_CHANGE_IA bit in ALL_INT_SRC is set for about 1.2 ms. This bit can be routed to the INT2 pin using the INT2_SLEEP_CHG bit in CTRL5_INT2_PAD_CTRL.

[ZAIDS-S23]

Hi @Federica Bossi 

Yes, you are right, the requirement of the LIR bit being 0 is a limitation for me, as I want to set it to 1 for the use of the FIFO in bypass-continuous mode. 

However, you're saying that I can enable the SLEEP_STATE_CHG interrupt on INT2 and it will be functional, even if the LIR bit is 1?

[Federica Bossi · Accepted solution]

Hi @ZAIDS-S23 ,

Yes, it is possible 🙂