2017-12-05 04:15 AM
hi,
I'm trying to program a LIS2DH via I2C, with a stm32l151rb. I'm interested in the activity mode, in order to wake up the stm32l1 using the INT2 pin connected to one micro's wake-up pin.
my configuration is:
/*CTRL_REG1*/ 0x29, //0b0010 1001 ODR@10Hz, LowPower mode enabled, Z disabled, Y disabled, X enabled, should drain 3uA
/*CTRL_REG2*/ 0x00, /*CTRL_REG3*/ 0x00, //disable all INT1 interrupts /*CTRL_REG4*/ 0x10, //0b0001 0000 FS = +/- 4G, self test disabled /*CTRL_REG5*/ 0x00, //do not latch /*CTRL_REG6*/ 0x08, //0b0000 1000 enable activity interrupt on INT2 /*REFERENCE*/ 0x00, //was 0x1e/*INT2_CFG*/ 0x02, //0b0000 0010 enable INT2 interrupt generation on X high events/*INT2_THS*/ 0x20, /*INT2_DUR*/ 0x10, /*ACT_THS*/ 0x21, //0x1e = 1000mG (9.81 m/s^2)@4G FS refer to table 84 (pg.48) of datasheet /*ACT_DUR*/ 0x14}; //0x01 = ~1 sec (900msec) refer to table 86 (pg.48) of datasheetINT2_THS and INT2_DUR are set as ACT regs just for debug.
I'm reading (for debug) the OUT_X/Y/Z_H regs and they behave meaningfully, just as INT2_SRC as I get a 0x16 whenever the X-axis exceeds the threshold. However, the IA, as the INT2 pin, is always low.
what configuration am I missing?
#lis2dh #activity #int22017-12-05 06:01 AM
I think, you are mixing two features:
- interrupt generator 2 which is configured by INT2_CFG, INT2_THS, INT2_DUR registers- activity/inactivity detection, configured by ACT_THS, ACT_DUR registers
Activity/Inactivity detection is able to detect if the device is still and automatically reduce the ODR to 10 Hz and so reduce power consumption. But because you are using ODR 10Hz as default configuration the activity/inactivity feature is useless for you in this case. The status of acitivity/inactivity feature is linked to INT2 by settings CTRL_REG6 = 0x08, and it is functional (I have validated it).
You configuration of interrupt generator 2 set the threshold to 1000mg and duration 1.6s so to trigger the interrupt you need to generate acceleration higher than 1g in X axis for more than 1.6s. 1g can be a problem, maybe you should reduce it to 0.8g for example. Than you should see that the IA bit in INT1_SRC is set. To link the status of interrupt generator 2 to INT2 pin you should set the CTRL_REG6 to 0x20.
2017-12-05 08:23 AM
thanks Miroslav for your quick response,
as I said, many of the configurations are kept for debug, but I sense from your reply that these conflict with each other, don't they actually?
For what concerns che interrupt generations, are you sure that the interrupt is triggered after 1.6 secs? as per
, page 53, the interrupt should be triggered instantly after passing the threshold and not after the duration, which instead happens on return-to-sleep.I shall make some tests in the direction you pointed out and get back to you. Thank you very much in the meantime.
2017-12-06 08:48 AM
Hi Miroslav,
I made some tests but had no luck.
I tried to invert the polarity a few times to see if the accelerometer is able to drive the line correctly as it actually does.
I disabled the activity mode and then put the configuration:
/*CTRL_REG1*/ 0x29, //0b0010 1001 ODR@10Hz, LowPower mode enabled, Z disabled, Y disabled, X enabled, should drain 3uA
/*CTRL_REG2*/ 0x00 /*CTRL_REG3*/ 0x00, //disable all INT1 interrupts /*CTRL_REG4*/ 0x10, //0b0001 0000 FS = +/- 4G, self test disabled /*CTRL_REG5*/ 0x02, //do latch on int2 /*CTRL_REG6*/ 0x62, //0b0--0 0010 enable interrupts on INT2, disable activity interrupt on INT2, polarity inversed /*REFERENCE*/ 0x00, //was 0x1e/*INT2_CFG*/ 0x02, //0b0000 0010 enable INT2 interrupt generation on X high events /*INT2_THS*/ 0x20, /*INT2_DUR*/ 0x02, //lowered duration /*CLICK_CFG*/ 0x00, /*CLICK_SRC*/ 0x00, /*CLICK_THS*/ 0x00, /*TIME_LIMIT*/ 0x00, /*TIME_LATENCY*/ 0x00, /*TIME_WINDOW*/ 0x00, /*ACT_THS*/ 0x00, //disabled, 0x1e = 1000mG (9.81 m/s^2)@4G FS refer to table 84 (pg.48) of datasheet /*ACT_DUR*/ 0x00}; //disabled, 0x01 = ~1 sec (900msec) refer to table 86 (pg.48) of datasheetI don't think I get the meaning of interrupt function1 and 2 in reg6, I've found no documentation on the topic, could you help on that? I have test any of the three configurations (01,10,11) but the result is the same.
I have also set the latch on INT2 to see whether the INT2 pin differs in any way from the internal state of the lis2dh. I cyclically check the INT2_SRC, with this code:
while (1)
{ uint8_t ret, res_int; ret=mems_ReadMem_B(ACCELReg_INT2_SRC, &res_int); if ((res_int&0x42) != 0) { ret=mems_ReadMem_B(ACCELReg_INT2_SRC, &res_int); } (void) ret; }The code double-checks the IA and the XH and the IA bits in the INT2_SRC, the second read should assure that the IA bit is cleared. That register behaves somehow wierdly:
2017-12-07 06:55 AM
Please decrease the threshold (
INT2_THS)
as I recommend you in my previous post, otherwise to trigger the interrupt you have to generate acceleration in X axis >1g for at least 200ms.2017-12-11 08:39 AM
turned out that Gravity LIS2DH kit has wrong labels on it. they just inverted INT1 & INT2!!
I got to it by seeing that INT2_SRC was moving correctly while the pin didn't.
thanks ​ for the big help on the topic, toby exlaining the correct use of INT2.