IIS3DWB INT1 / INT2 stopping/stuck at high after several Watermark events

[TElle.1]

Hi there,

we are using two IIS3DWB (but the problem also occurs when only using one sensor) and trying to read out data from fifo when a certain watermark/threshold is reached.

When polling the status register this works, but causes a lot of SPI traffic. And since both sensors share the same SPI (separate CS), we like to use INT1 (or INT2) instead of polling.

Therefore we configured INT1 to trigger on WTM. This works fine for several times, but suddenly it stops generating interrupts and is stuck at high (verified with oscilloscope) until sensor is completely reset.

Do you have any hint whats going wrong or some demo code for watermark threshold and INT1?

Here is how we configure the sensor (Python syntax):

sens.reset_set(iis3.PROPERTY_ENABLE)
while(sens.reset_get()):    # Wait until reset is done
    pass
 
# Turn on measurement
sens.block_data_update_set(iis3.PROPERTY_ENABLE)
sens.xl_data_rate_set(iis3.IIS3DWB_XL_ODR_26k7Hz)
 
sens.xl_full_scale_set(iis3.IIS3DWB_8g)
 
sens.xl_hp_path_on_out_set(iis3.IIS3DWB_LP_ODR_DIV_100);
sens.xl_filter_lp2_set(iis3.PROPERTY_ENABLE);
 
# Enable Timestamping
sens.timestamp_set(iis3.PROPERTY_ENABLE)
 
# Enable Temperature to FIFO
sens.fifo_temp_batch_set(iis3.IIS3DWB_TEMP_BATCHED_AT_104Hz)
 
# enable timestamp to fifo
sens.fifo_timestamp_decimation_set(iis3.IIS3DWB_DEC_8)
 
# Rounding Mode for Block read
sens.rounding_mode_set(iis3.IIS3DWB_ROUND)# does not work as expected ?
 
# Watermark threshold
sens.fifo_watermark_set(200)    # Trigger when 200 samples are read into buffer
 
# Enable streaming to fifo
sens.fifo_xl_batch_set(iis3.IIS3DWB_XL_BATCHED_AT_26k7Hz)
sens.fifo_mode_set(iis3.IIS3DWB_STREAM_TO_FIFO_MODE)
 
sens.pin_int2_route_set(sens.BIT_INT1_FIFO_TH | sens.BIT_INT1_FIFO_FULL)

Each time a INT1 occurs, we perform the following:

#INT1 ISR 
    fill=sens.fifo_data_level_get() 
    res=sens.fifo_block_get(fill)
 
#---- We read all data in one SPI frame:
fifo_block_get(self,size):
        ret = self.__read_reg(self.IIS3DWB_FIFO_DATA_OUT_TAG,7*size)
        return ret
 

Any ideas/hints what is going wrong?

Regards,

Tobias Ellermeyer

[Eleon BORLINI]

Hi @TElle.1​ , are you polling the FIFO_WTM_IA bit of FIFO_STATUS2 register, right? And are you setting the INT1 or the INT2 pin for the interrupt? Because in this code line the int2 is declared in the function but the INT1 is enabled...

sens.pin_int2_route_set(sens.BIT_INT1_FIFO_TH | sens.BIT_INT1_FIFO_FULL)

Or you could try another way... did you (try to) set the STOP_ON_WTM bit in FIFO_CTRL2 (08h) register? This to prevent the refill of the FIFO while you are reading it, and to avoid an eventual superimposition of interrupts. Since the IIS3DWB ODR speed is quite high (26.7kHz), it could be the case of a clock conflict, especially if the SPI is running at low frequencies (which is the speed of your SPI communication? Does the interrupt stuck occur at the same rate both in the single IIS3DWB case and in the two IIS3DWBs one?) Regards