Having problems getting compression to work on the LSM6DSOX

DFors.1 · ‎2020-05-19

Trying to enable compression. I only see tags 0x01 and 0x02, none of the compression tags.

bellow is my reg inits.

#define IMU_READ_BIT      0x80
 
#define EMB_FUNC_EN_B     0x05
#define FIFO_CTRL1        0x07
#define FIFO_CTRL2        0x08
#define FIFO_CTRL3        0x09
#define FIFO_CTRL4        0x0A
#define INT1_CTRL         0x0D
#define IMU_REG_WHO_AM_I  0x0F
#define CTRL1_XL          0x10
#define CTRL2_G           0x11
#define FIFO_STATUS1      0x3A
#define FIFO_STATUS2      0x3B
#define EMB_FUNC_INIT_B   0x67
#define FIFO_DATA_OUT_TAG 0x78
 
#define FIFO_WATERMARK    0x18B
 
void setupIMU(spi_device_handle_t spi) {
    writeIMURegister(spi, FIFO_CTRL4, 0x00); // Disable FIDO for configuration
    writeIMURegister(spi, FIFO_CTRL3, 0x44); // Gyroscope 104Mhz, Accelerometer 104MHz
    writeIMURegister(spi, CTRL1_XL,   0x40); // Accelerometer 104MHz, 2g
    writeIMURegister(spi, CTRL2_G,    0x40); // Gyroscope 104Mhz, 250 dps
    writeIMURegister(spi, FIFO_CTRL1, (FIFO_WATERMARK & 0xff)); //fifo watermark
    writeIMURegister(spi, FIFO_CTRL2, 0x40 | ((FIFO_WATERMARK & 0x100) >>8)); //compression on, bit 9 of fifo watermark
    writeIMURegister(spi, EMB_FUNC_EN_B, 0x08); //compression on
//    writeIMURegister(spi, EMB_FUNC_INIT_B, 0x80); //init compression
    writeIMURegister(spi, INT1_CTRL,  0x38); //INT1 on FIFO threshold DDF set for FIFO_FULL, FIFO_OVR, and FIFO_TH
    writeIMURegister(spi, FIFO_CTRL4, 0x06); //Continuous mode 
}

Some of the FIDO entries I expected compression on.

01-0: 0C 00 D3 FF 24 00

02-2: DF 73 E4 F5 D0 00

01-3: 0D 00 EC FF 63 00

02-3: DF 6C E4 EB D0 00

01-1: 08 00 D4 FF 31 00

02-2: DF 7E E4 FF D0 00

01-2: 05 00 F6 FF 5F 00

02-1: DF 68 E4 05 D1 00

01-0: 0C 00 CE FF 2C 00

02-1: DF 81 E4 ED D0 00

01-3: 0B 00 E6 FF 31 00

02-1: DF 66 E4 FF D0 00

01-1: 0C 00 EE FF 58 00

02-0: DF 75 E4 E0 D0 00

01-2: 09 00 E1 FF 42 00

02-0: DF 74 E4 F6 D0 00

01-0: 06 00 F7 FF 4F 00

02-2: DF 60 E4 0A D1 00

01-3: 14 00 C8 FF 2A 00

02-3: DF 88 E4 FA D0 00

01-1: 0E 00 E8 FF 35 00

02-1: DF 79 E4 F9 D0 00

01-2: 10 00 E0 FF 41 00

02-3: DF 70 E4 DF D0 00

01-0: 0C 00 E4 FF 5D 00

02-2: DF 6D E4 00 D1 00

Dwayne

DFors.1 · ‎2020-09-02

Yes, I failed to switch to the embedded register page....

        writeIMURegister(spiImu, FUNC_CFG_ACCESS, 0x80); //Switch to embedded regs
        writeIMURegister(spiImu, EMB_FUNC_EN_B,   0x08); //compression on
        writeIMURegister(spiImu, FUNC_CFG_ACCESS, 0x00); //Switch to standard regs

View solution in original post

Eleon BORLINI · ‎2020-05-20

Hi @DFors.1 , are you writing the FIFO control registers but you cannot read back the value you have written? Or is the FIFO compression not working, even if you are able to write registers in a stable way? Reporting the datasheet instructions (p.38) on this topic, you can do some tests trying to force writing non-compressed data at a selectable rate using the UNCOPTR_RATE_[1:0] field in FIFO_CTRL2 (08h), and checking if you see some difference.

In order to maximize the amount of accelerometer and gyroscope data in FIFO, the user can enable the compression algorithm by setting to 1 both the FIFO_COMPR_EN bit in EMB_FUNC_EN_B (05h) (embedded functions registers bank) and the FIFO_COMPR_RT_EN bit in FIFO_CTRL2 (08h). When compression is enabled, it is also possible to force writing non-compressed data at a selectable rate using the UNCOPTR_RATE_[1:0] field in FIFO_CTRL2 (08h).

Regards

DFors.1 · ‎2020-05-20

FIFO compression is not working for me, All the FIFO tag TAG_SENSOR fields are 0x01 or 0x02. Compression would generate TAG_SENSOR fields of 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, and/or 0x0D,
I'm able to read the registers back, and verify they are set to the values I wrote. I have verified I can read and write the registers.
you can do some tests trying to force writing non-compressed data at a selectable rate using the UNCOPTR_RATE_[1:0] field in FIFO_CTRL2 (08h), and checking if you see some difference. My data is does not show any compress TAG_SENSOR values, not sure how this would help debug.
the user can enable the compression algorithm by setting to 1 both the FIFO_COMPR_EN bit in EMB_FUNC_EN_B (05h) (embedded functions registers bank) and the FIFO_COMPR_RT_EN bit in FIFO_CTRL2 (08h). Yes, I think I'm doing this lines 25 and 25 in the code above.
I have been reading through "AN5272 application note", and the "LSM6DSOX DataSheet" and can not identify what I'm doing wrong.

DFors.1 · ‎2020-05-26

@Eleon BORLINI Do you have an example of the register settings you know enable the compression?

Eleon BORLINI · ‎2020-06-01

@DFors.1 , did you already check the C library available on github lsm6dsox_compressed_fifo.c? The settings for the FIFO compression are coded here below. Regards

 /* Restore default configuration */
  lsm6dsox_reset_set(&dev_ctx, PROPERTY_ENABLE);
  do {
    lsm6dsox_reset_get(&dev_ctx, &rst);
  } while (rst);
 
  /* Disable I3C interface */
  lsm6dsox_i3c_disable_set(&dev_ctx, LSM6DSOX_I3C_DISABLE);
 
  /* Enable Block Data Update */
  lsm6dsox_block_data_update_set(&dev_ctx, PROPERTY_ENABLE);
 
  /* Set full scale */
  lsm6dsox_xl_full_scale_set(&dev_ctx, LSM6DSOX_2g);
  lsm6dsox_gy_full_scale_set(&dev_ctx, LSM6DSOX_2000dps);
 
  /*
   * Set FIFO watermark (number of unread sensor data TAG + 6 bytes
   * stored in FIFO) to FIFO_WATERMARK samples
   */
  lsm6dsox_fifo_watermark_set(&dev_ctx, FIFO_WATERMARK);
 
  /* Set FIFO batch XL/Gyro ODR to 12.5Hz */
  lsm6dsox_fifo_xl_batch_set(&dev_ctx, LSM6DSOX_XL_BATCHED_AT_12Hz5);
  lsm6dsox_fifo_gy_batch_set(&dev_ctx, LSM6DSOX_GY_BATCHED_AT_12Hz5);
 
  /* Set FIFO mode to Stream mode (aka Continuous Mode) */
  lsm6dsox_fifo_mode_set(&dev_ctx, LSM6DSOX_STREAM_MODE);
 
  /* Enable FIFO compression on all samples */
  lsm6dsox_compression_algo_set(&dev_ctx, LSM6DSOX_CMP_DISABLE);
 
  /* Enable drdy 75 μs pulse: uncomment if interrupt must be pulsed */
  //lsm6dsox_data_ready_mode_set(&dev_ctx, LSM6DSOX_DRDY_PULSED);

DFors.1 · ‎2020-06-01

I ported your code over to my project....

void IMUInitialize(void) {
    stmdev_ctx_t dev_ctx;
    uint8_t whoamI, rst, intCtl;
 
  dev_ctx.write_reg = writeIMURegister;
  dev_ctx.read_reg = readIMURegister;
  dev_ctx.handle = initIMU();
 
  /* Check device ID */
  lsm6dsox_device_id_get(&dev_ctx, &whoamI);
  if (whoamI != LSM6DSOX_ID)
    while(1);
 
  /* Restore default configuration */
  lsm6dsox_reset_set(&dev_ctx, PROPERTY_ENABLE);
  do {
    lsm6dsox_reset_get(&dev_ctx, &rst);
  } while (rst);
 
  /* Disable I3C interface */
  lsm6dsox_i3c_disable_set(&dev_ctx, LSM6DSOX_I3C_DISABLE);
 
  /* Enable Block Data Update */
  lsm6dsox_block_data_update_set(&dev_ctx, PROPERTY_ENABLE);
 
  /* Set full scale */
  lsm6dsox_xl_full_scale_set(&dev_ctx, LSM6DSOX_2g);
  lsm6dsox_gy_full_scale_set(&dev_ctx, LSM6DSOX_2000dps);
 
  /*
   * Set FIFO watermark (number of unread sensor data TAG + 6 bytes
   * stored in FIFO) to FIFO_WATERMARK samples
   */
  lsm6dsox_fifo_watermark_set(&dev_ctx, FIFO_WATERMARK);
 
  /* Set FIFO batch XL/Gyro ODR to 12.5Hz */
  lsm6dsox_fifo_xl_batch_set(&dev_ctx, LSM6DSOX_XL_BATCHED_AT_12Hz5);
  lsm6dsox_fifo_gy_batch_set(&dev_ctx, LSM6DSOX_GY_BATCHED_AT_12Hz5);
 
  /* Set FIFO mode to Stream mode (aka Continuous Mode) */
  lsm6dsox_fifo_mode_set(&dev_ctx, LSM6DSOX_STREAM_MODE);
 
  /* Enable FIFO compression on all samples */
  lsm6dsox_compression_algo_set(&dev_ctx, LSM6DSOX_CMP_DISABLE);
 
  /* Enable drdy 75 μs pulse: uncomment if interrupt must be pulsed */
  //lsm6dsox_data_ready_mode_set(&dev_ctx, LSM6DSOX_DRDY_PULSED);
 
  /*
   * FIFO watermark interrupt routed on INT1 pin
   * WARNING: INT1 pin is used by sensor to switch in I3C mode.
   */
  //lsm6dsox_pin_int1_route_get(&dev_ctx, &int1_route);
  //int1_route.reg.int1_ctrl.int1_fifo_th = PROPERTY_ENABLE;
  //lsm6dsox_pin_int1_route_set(&dev_ctx, &int1_route);
  /*  FIFO watermark interrupt routed on INT1 pin */
 
  /* FIFO watermark interrupt routed on INT2 pin */
  //lsm6dsox_pin_int2_route_get(&dev_ctx, &int2_route);
  //int2_route.reg.int2_ctrl.int2_fifo_th = PROPERTY_ENABLE;
  //lsm6dsox_pin_int2_route_set(&dev_ctx, &int2_route);
 
  /* Set Output Data Rate */
  lsm6dsox_xl_data_rate_set(&dev_ctx, LSM6DSOX_XL_ODR_12Hz5);
  lsm6dsox_gy_data_rate_set(&dev_ctx, LSM6DSOX_GY_ODR_12Hz5);
  lsm6dsox_fifo_timestamp_decimation_set(&dev_ctx, LSM6DSOX_DEC_1);
  lsm6dsox_timestamp_set(&dev_ctx, PROPERTY_ENABLE);
}

running it I do not see any compression FIFO tags of the data, just uncompressed 0x01, 0x02 and 0x04 records in the fifo.

Is there a variant of the hardware without the compression feature that I might have got by error?

01-1: 02 00 FC FF 07 00
02-1: A9 3E 6F F6 91 03
04-2: 68 16 08 00 00 11
01-2: 02 00 FB FF 07 00
02-2: A9 3E 6F F6 92 03
04-0: 68 22 08 00 00 11
01-0: 02 00 FC FF 07 00
02-0: AF 3E 70 F6 9A 03
04-3: 68 2E 08 00 00 11
01-3: 02 00 FB FF 07 00
02-3: A9 3E 69 F6 95 03
04-1: 68 3A 08 00 00 11
01-1: 02 00 FB FF 07 00
02-1: A9 3E 6B F6 95 03
04-2: 68 46 08 00 00 11
01-2: 02 00 FC FF 07 00
02-2: A7 3E 69 F6 97 03
04-0: 68 52 08 00 00 11
01-0: 02 00 FB FF 07 00
02-0: A7 3E 70 F6 94 03
04-3: 68 5E 08 00 00 11
01-3: 02 00 FB FF 07 00
02-3: AA 3E 6E F6 9C 03
04-1: 68 6A 08 00 00 11
01-1: 02 00 FB FF 07 00
02-1: AC 3E 6C F6 97 03
04-2: 68 76 08 00 00 11
01-2: 02 00 FC FF 07 00
02-2: AE 3E 71 F6 97 03
04-0: 68 82 08 00 00 11
01-0: 02 00 FB FF 07 00
02-0: AB 3E 6A F6 92 03
04-3: 68 8E 08 00 00 11
01-3: 02 00 FC FF 07 00
02-3: AA 3E 71 F6 99 03
04-1: 68 9A 08 00 00 11
01-1: 02 00 FC FF 07 00
02-1: A3 3E 6B F6 99 03
04-2: 68 A6 08 00 00 11
01-2: 02 00 FC FF 07 00
02-2: A9 3E 71 F6 92 03
04-0: 68 B2 08 00 00 11
01-0: 02 00 FC FF 07 00
02-0: AD 3E 74 F6 99 03
04-3: 68 BE 08 00 00 11
01-3: 02 00 FB FF 07 00
02-3: AD 3E 6C F6 94 03
04-1: 68 CA 08 00 00 11
01-1: 02 00 FB FF 07 00
02-1: A8 3E 71 F6 98 03
04-2: 68 D6 08 00 00 11
01-2: 02 00 FC FF 07 00
02-2: AF 3E 6F F6 99 03
04-0: 68 E2 08 00 00 11
01-0: 02 00 FB FF 07 00
02-0: AC 3E 71 F6 9A 03
04-3: 68 EE 08 00 00 11
01-3: 02 00 FC FF 07 00
02-3: AA 3E 69 F6 9F 03
04-1: 68 FA 08 00 00 11
01-1: 02 00 FB FF 07 00
02-1: A8 3E 6D F6 97 03
04-2: 68 06 09 00 00 11
01-2: 02 00 FB FF 07 00
02-2: A9 3E 72 F6 9A 03
04-0: 68 12 09 00 00 11
01-0: 02 00 FC FF 07 00
02-0: AF 3E 6C F6 93 03
04-3: 68 1E 09 00 00 11
01-3: 02 00 FB FF 07 00
02-3: AF 3E 6E F6 96 03
04-1: 68 2A 09 00 00 11
01-1: 02 00 FC FF 07 00
02-1: B2 3E 71 F6 9A 03
04-2: 68 36 09 00 00 11
01-2: 02 00 FB FF 07 00
02-2: AA 3E 6E F6 97 03
04-0: 68 42 09 00 00 11
01-0: 02 00 FB FF 07 00
02-0: B0 3E 73 F6 95 03
04-3: 68 4E 09 00 00 11
01-3: 02 00 FB FF 07 00
02-3: A8 3E 6F F6 98 03
04-1: 68 5A 09 00 00 11
01-1: 02 00 FB FF 07 00
02-1: A9 3E 6B F6 95 03
04-2: 68 66 09 00 00 11
01-2: 02 00 FC FF 07 00
02-2: AE 3E 6E F6 9D 03
04-0: 68 72 09 00 00 11
01-0: 02 00 FC FF 07 00
02-0: A0 3E 6B F6 95 03
04-3: 68 7E 09 00 00 11
01-3: 02 00 FC FF 07 00
02-3: AE 3E 6C F6 98 03
04-1: 68 8A 09 00 00 11
01-1: 02 00 FB FF 07 00
02-1: A9 3E 74 F6 95 03
04-2: 68 96 09 00 00 11
01-2: 02 00 FC FF 07 00
02-2: AF 3E 6E F6 96 03
04-0: 68 A2 09 00 00 11
01-0: 02 00 FB FF 07 00
02-0: AA 3E 72 F6 97 03
04-3: 68 AE 09 00 00 11
01-3: 02 00 FB FF 07 00
02-3: AC 3E 6D F6 99 03
04-1: 68 BA 09 00 00 11
01-1: 02 00 FC FF 07 00
02-1: A6 3E 6D F6 93 03
04-2: 68 C6 09 00 00 11
01-2: 02 00 FB FF 07 00
02-2: A8 3E 6E F6 9B 03
04-0: 68 D2 09 00 00 11
01-0: 02 00 FC FF 07 00
02-0: AA 3E 6E F6 93 03
04-3: 68 DE 09 00 00 11
01-3: 02 00 FC FF 07 00
02-3: A9 3E 6F F6 98 03
04-1: 68 EA 09 00 00 11
01-1: 02 00 FB FF 07 00
02-1: AA 3E 72 F6 98 03
04-2: 68 F6 09 00 00 11
01-2: 02 00 FC FF 07 00
02-2: A9 3E 72 F6 97 03
04-0: 68 02 0A 00 00 11
01-0: 02 00 FB FF 07 00
02-0: AA 3E 71 F6 9C 03
04-3: 68 0E 0A 00 00 11
01-3: 02 00 FB FF 07 00
02-3: A7 3E 71 F6 99 03
04-1: 68 1A 0A 00 00 11
01-1: 02 00 FB FF 07 00
02-1: A5 3E 75 F6 9D 03
04-2: 68 26 0A 00 00 11
01-2: 02 00 FB FF 07 00
02-2: A4 3E 6D F6 9A 03
04-0: 68 32 0A 00 00 11
01-0: 02 00 FB FF 07 00
02-0: A7 3E 75 F6 97 03
04-3: 68 3E 0A 00 00 11
01-3: 02 00 FB FF 07 00
02-3: A6 3E 6D F6 9C 03
04-1: 68 4A 0A 00 00 11
01-1: 02 00 FC FF 07 00
02-1: A5 3E 6B F6 9B 03
04-2: 68 56 0A 00 00 11
01-2: 02 00 FB FF 07 00
02-2: AA 3E 73 F6 9B 03
04-0: 68 62 0A 00 00 11
01-0: 02 00 FB FF 07 00
02-0: AD 3E 6B F6 96 03
04-3: 68 6E 0A 00 00 11
01-3: 02 00 FC FF 07 00
02-3: AA 3E 72 F6 9A 03
04-1: 68 7A 0A 00 00 11
01-1: 02 00 FB FF 07 00
02-1: A9 3E 6F F6 9A 03
04-2: 68 86 0A 00 00 11
01-2: 02 00 FB FF 07 00
02-2: A2 3E 6F F6 97 03
04-0: 68 92 0A 00 00 11
01-0: 02 00 FB FF 07 00
02-0: A8 3E 70 F6 9A 03
04-3: 68 9E 0A 00 00 11
01-3: 02 00 FB FF 07 00
02-3: A9 3E 6E F6 99 03
04-1: 68 AA 0A 00 00 11
01-1: 02 00 FB FF 07 00
02-1: B0 3E 6F F6 97 03
04-2: 68 B6 0A 00 00 11
01-2: 02 00 FB FF 07 00
02-2: A2 3E 6E F6 9C 03
04-0: 68 C2 0A 00 00 11
01-0: 02 00 FB FF 07 00
02-0: AA 3E 70 F6 98 03
04-3: 68 CE 0A 00 00 11
01-3: 02 00 FB FF 07 00
02-3: A6 3E 70 F6 96 03
04-1: 68 DA 0A 00 00 11
01-1: 02 00 FB FF 07 00
02-1: AB 3E 6B F6 9A 03
04-2: 68 E6 0A 00 00 11
01-2: 02 00 FB FF 07 00
02-2: AA 3E 6D F6 96 03
04-0: 68 F2 0A 00 00 11
01-0: 02 00 FC FF 07 00
02-0: A9 3E 6F F6 9B 03
04-3: 68 FE 0A 00 00 11
01-3: 02 00 FB FF 07 00
02-3: AB 3E 6F F6 9A 03
04-1: 68 0A 0B 00 00 11
01-1: 02 00 FC FF 07 00
02-1: AE 3E 6F F6 96 03
04-2: 68 16 0B 00 00 11
01-2: 02 00 FB FF 07 00
02-2: A7 3E 72 F6 9B 03
04-0: 68 22 0B 00 00 11
01-0: 02 00 FB FF 07 00
02-0: A3 3E 6E F6 97 03
04-3: 68 2E 0B 00 00 11
01-3: 02 00 FC FF 07 00
02-3: A9 3E 71 F6 9A 03
04-1: 68 3A 0B 00 00 11
01-1: 02 00 FB FF 07 00
02-1: AB 3E 70 F6 97 03
04-2: 68 46 0B 00 00 11
01-2: 02 00 FB FF 07 00
02-2: A5 3E 74 F6 9A 03
04-0: 68 52 0B 00 00 11
01-0: 02 00 FC FF 07 00
02-0: A9 3E 72 F6 96 03
04-3: 68 5E 0B 00 00 11
01-3: 02 00 FB FF 07 00
02-3: A6 3E 73 F6 97 03
04-1: 68 6A 0B 00 00 11
01-1: 02 00 FB FF 07 00
02-1: A7 3E 71 F6 9C 03
04-2: 68 76 0B 00 00 11
01-2: 02 00 FB FF 07 00
02-2: A5 3E 6D F6 99 03
04-0: 68 82 0B 00 00 11
01-0: 02 00 FC FF 07 00
02-0: A7 3E 6D F6 96 03
04-3: 68 8E 0B 00 00 11
01-3: 02 00 FB FF 07 00
02-3: AA 3E 6F F6 97 03
04-1: 68 9A 0B 00 00 11
01-1: 02 00 FB FF 07 00
02-1: AA 3E 6F F6 99 03
04-2: 68 A6 0B 00 00 11
01-2: 02 00 FB FF 07 00
02-2: A7 3E 70 F6 9B 03
04-0: 68 B2 0B 00 00 11
01-0: 02 00 FB FF 07 00
02-0: A7 3E 6C F6 9A 03
04-3: 68 BE 0B 00 00 11
01-3: 02 00 FB FF 07 00
02-3: AC 3E 6D F6 9D 03
04-1: 68 CA 0B 00 00 11
01-1: 02 00 FB FF 07 00
02-1: AB 3E 70 F6 98 03
04-2: 68 D6 0B 00 00 11
01-2: 02 00 FC FF 07 00
02-2: A7 3E 72 F6 9A 03
04-0: 68 E2 0B 00 00 11
01-0: 02 00 FB FF 07 00
02-0: A6 3E 6E F6 99 03
04-3: 68 EE 0B 00 00 11
01-3: 02 00 FB FF 07 00
02-3: A8 3E 71 F6 9E 03
04-1: 68 FA 0B 00 00 11
01-1: 02 00 FB FF 07 00
02-1: AC 3E 6F F6 9D 03
04-2: 68 06 0C 00 00 11
01-2: 02 00 FC FF 07 00
02-2: AB 3E 6E F6 A0 03
04-0: 68 12 0C 00 00 11
01-0: 02 00 FC FF 07 00
02-0: A5 3E 6E F6 9B 03
04-3: 68 1E 0C 00 00 11
01-3: 02 00 FB FF 07 00
02-3: AC 3E 6F F6 9A 03
04-1: 68 2A 0C 00 00 11
01-1: 02 00 FB FF 07 00
02-1: AF 3E 6E F6 98 03
04-2: 68 36 0C 00 00 11
01-2: 02 00 FB FF 07 00
02-2: A3 3E 70 F6 9B 03
04-0: 68 42 0C 00 00 11
01-0: 02 00 FB FF 07 00

DFors.1 · ‎2020-06-01

ordered Digikey 497-18364-ND

STEVAL-MKI197V1

LSM6DSOX - Accelerometer, Gyroscope, 3 Axis Sensor Evaluation Board

I'm working from Home, unable to read the chip markings with my eyes or cellphone camera. Would have to take it into the lab (wrok office) to read it.

Eleon BORLINI · ‎2020-09-02

Hi @DFors.1 , were you able to fix this issue? I suggest you to check also the FIFO decompression utility on Github at this link.

Regards

DFors.1 · ‎2020-09-02

Yes, I failed to switch to the embedded register page....

        writeIMURegister(spiImu, FUNC_CFG_ACCESS, 0x80); //Switch to embedded regs
        writeIMURegister(spiImu, EMB_FUNC_EN_B,   0x08); //compression on
        writeIMURegister(spiImu, FUNC_CFG_ACCESS, 0x00); //Switch to standard regs