Hi @VSavenia ,
meaning "decimation" the decreases the sample rate of a signal by removing samples from the data stream, there are some possible ways it is usually possible reduce the ODR, even if not possible for the IIS3DWB.
You could however apply a low pass filter to the output data chain: you can enable it by configuring the HPCF_XL_[2:0] bits in CTRL8_XL (17h) register. In this way you could reduce also the reading rate of the output from master side, instead of performing a decimation in post processing.
There is another kind of decimation that you can implement on the IIS3DWB, that is the decimation for timestamp batching in FIFO. You can enable it by configuring the DEC_TS_ BATCH[1:0] bits in FIFO_CTRL4 (0Ah) register, as described in the datasheet p. 29.
-Eleon
