Problems with TX using S2-LP - without HAL libraries

[RLind.3]

Hi there,

I'm running into some weird problems while trying to use the S2-LP transceiver. It seems as though the transceiver is only sending one byte each time it enters TX mode.

I am writing a program for a heavily storage-constrained project and as such I am not using any of the HAL libraries. I know that SPI is working because I am able to write to the transceiver, change its state, set interrupts, and read from its registers.

I am using the S2868A2 expansion board with a NUCLEO-L010RB development board.

I used the STSW-S2LP-DK as a proof of concept that the S2-LP was capable of sending the packets I wanted. That worked fine, so I exported the configuration and put it into my program.

The problem I am running into is when I write 12 bytes (my payload size) to the TX FIFO and send the TX command, the S2-LP seems to only send one byte - when I read back the TX_FIFO_STATUS register it says the FIFO still has 11 bytes in it, and the FIFO_ALMOST_EMPTY interrupt only fires when I flush the TX buffer. What am I doing wrong?

I have tried writing varying lengths of data to the FIFO and each time I enter TX mode it only seems to send one byte.

To be clear, my process is:

1. Flush TX FIFO
2. Write data to TX FIFO
3. Send TX command

// Configuration code (mostly from STSW-S2LP-DK)
 
tmp[0] = 0x33;
spi_write(TRX_S2_LP, 0x01, tmp, 1); // Set S2-LP GPIO1 to interrupt when TX/RX FIFO is almost empty
 
tmp[0] = 0xA3; /* reg. GPIO3_CONF (0x03) */
spi_write(TRX_S2_LP, 0x03, tmp, 1);
tmp[0] = 0x62; /* reg. SYNT3 (0x05) */
tmp[1] = 0x3B; /* reg. SYNT2 (0x06) */
tmp[2] = 0x72; /* reg. SYNT1 (0x07) */
tmp[3] = 0xE2; /* reg. SYNT0 (0x08) */
tmp[4] = 0x2F; /* reg. IF_OFFSET_ANA (0x09) */
tmp[5] = 0xC2; /* reg. IF_OFFSET_DIG (0x0A) */
spi_write(TRX_S2_LP, 0x05, tmp, 6);
tmp[0] = 0x92; /* reg. MOD4 (0x0E) */
tmp[1] = 0xA6; /* reg. MOD3 (0x0F) */
tmp[2] = 0x23; /* reg. MOD2 (0x10) */
tmp[3] = 0x01; /* reg. MOD1 (0x11) */
tmp[4] = 0x06; /* reg. MOD0 (0x12) */
tmp[5] = 0x13; /* reg. CHFLT (0x13) */
spi_write(TRX_S2_LP, 0x0E, tmp, 6);
tmp[0] = 0x56; /* reg. RSSI_TH (0x18) */
spi_write(TRX_S2_LP, 0x18, tmp, 1);
tmp[0] = 0x55; /* reg. ANT_SELECT_CONF (0x1F) */
spi_write(TRX_S2_LP, 0x1F, tmp, 1);
tmp[0] = 0x40; /* reg. PCKTCTRL6 (0x2B) */
tmp[1] = 0xB4; /* reg. PCKTCTRL5 (0x2C) */
tmp[2] = 0x00; /* reg. PCKTCTRL4 (0x2D) */
spi_write(TRX_S2_LP, 0x2B, tmp, 3);
tmp[0] = 0x01; /* reg. PCKTCTRL3 (0x2E) */
tmp[1] = 0x00; /* reg. PCKTCTRL2 (0x2F) */
spi_write(TRX_S2_LP, 0x2E, tmp, 2);
tmp[0] = 0x00; /* reg. PCKTCTRL1 (0x30) */
spi_write(TRX_S2_LP, 0x30, tmp, 1);
tmp[0] = 0x0C; /* reg. PCKTLEN0 (0x32) */
tmp[1] = 0x00; /* reg. SYNC3 (0x33) */
tmp[2] = 0x00; /* reg. SYNC2 (0x34) */
tmp[3] = 0xB3; /* reg. SYNC1 (0x35) */
tmp[4] = 0x4D; /* reg. SYNC0 (0x36) */
tmp[5] = 0x21; /* reg. QI (0x37) */
spi_write(TRX_S2_LP, 0x32, tmp, 6);
tmp[0] = 0x01; /* reg. PROTOCOL1 (0x3A) */
spi_write(TRX_S2_LP, 0x3A, tmp, 1);
tmp[0] = 0x40; /* reg. FIFO_CONFIG3 (0x3C) */
tmp[1] = 0x40; /* reg. FIFO_CONFIG2 (0x3D) */
tmp[2] = 0x40; /* reg. FIFO_CONFIG1 (0x3E) */
tmp[3] = 0x01; /* reg. FIFO_CONFIG0 (0x3F) */
spi_write(TRX_S2_LP, 0x3C, tmp, 4);
tmp[0] = 0x00; /* reg. TIMERS5 (0x46) */
tmp[1] = 0x19; /* reg. TIMERS4 (0x47) */
spi_write(TRX_S2_LP, 0x46, tmp, 2);
tmp[0] = 0x21; /* reg. TIMERS2 (0x49) */
spi_write(TRX_S2_LP, 0x49, tmp, 1);
tmp[0] = 0x10; /* reg. IRQ_MASK3 (0x50) */
spi_write(TRX_S2_LP, 0x50, tmp, 1);
tmp[0] = 0x02; /* reg. IRQ_MASK1 (0x52) */
tmp[1] = 0x10; /* reg. IRQ_MASK0 (0x53) */
spi_write(TRX_S2_LP, 0x52, tmp, 2);
tmp[0] = 0x03; /* reg. PA_POWER8 (0x5A) */
spi_write(TRX_S2_LP, 0x5A, tmp, 1);
tmp[0] = 0x07; /* reg. PA_POWER0 (0x62) */
tmp[1] = 0x01; /* reg. PA_CONFIG1 (0x63) */
tmp[2] = 0x88; /* reg. PA_CONFIG0 (0x64) */
spi_write(TRX_S2_LP, 0x62, tmp, 3);
tmp[0] = 0x8B; /* reg. RCO_CALIBR_CONF3 (0x6E) */
tmp[1] = 0xCD; /* reg. RCO_CALIBR_CONF2 (0x6F) */
spi_write(TRX_S2_LP, 0x6E, tmp, 2);
tmp[0] = 0x9B; /* reg. PM_CONF3 (0x76) */
tmp[1] = 0xF4; /* reg. PM_CONF2 (0x77) */
spi_write(TRX_S2_LP, 0x76, tmp, 2);
 
 
 
// Code from main loop
 
uint8 data[] = {0xF0, 0xF0, 0x11, 0x9A, 0x22, 0xA9, 0x11, 0x84, 0xF0, 0x84, 0x0F, 0xF0};
spi_send_cmd(TRX_S2_LP, TRX_SPI_CMD_ABORT); // Not sure if this is necessary
spi_send_cmd(TRX_S2_LP, TRX_SPI_CMD_FLUSH_TX); // Flush FIFO
tick_delay(50);
spi_write(TRX_S2_LP, 0xFF, data, 12); // Write 12 bytes of data to FIFO
tx_data = spi_read(TRX_S2_LP, 0x8F); // Read length of data in FIFO
spi_send_cmd(TRX_S2_LP, TRX_SPI_CMD_TX); // Enter TX state
tick_delay(200);
tx_data = spi_read(TRX_S2_LP, 0x8F); // Read length of data in FIFO
tick_delay(2000);

Please let me know if you need any other information.

[RLind.3]

All of a sudden, without any code changes, it has started working. All I did was restart the debugger. I've tried deleting the question but it won't let me. Sorry for wasting anyone's time.