Hi,
I want to utilize the Chorus 10M Performance Monitor APU. In the reference-manual rm0004-programmers-reference-manual-for-book-e-processors-stmicroelectronics.pdf Section 3.16.3 Table 55 which shows the Mapping of the PMLCax Register bits you can see that bits 41-48 should contain a Event ID which according to EIS is device specific. But I cannot find any information regarding the supported events of the MCU. Can somebody provide a hint to the document which suppose to describe those Event IDs (Cache Hit/Miss etc.)?
PS: I already checked the device specific document rm0452-spc58-h-line--32-bit-power-architecture-automotive-mcu-triple-z4-cores-200-mhz-10-mbytes-flash-hsm-asild-stmicroelectronics.pdf but am unable to find any info regarding the PMU Events
BR Wadim
