2023-01-18 08:06 PM
There is a leak path between IN+ and VREF, through the feedback resistors when VREF is connected to GND.
I need to know whether this path is still possible when the IC has no VCC applied to it.
I disable the IC to save power consumption but if this path is still present in the absence of VCC, then I need to take other measures.
2023-06-06 08:46 AM
Hi,
Yes there is a pass even when the power is off.
You can find it fig 17 of the datasheet. (https://www.st.com/resource/en/datasheet/tsc210.pdf)
Best Regards,
Pierre