TDA7498 application schematics dillemas

[iloveasic]

Dear sir,madam,

I have a questions about schematics in figure 3 of TDA7498s datasheet:

- should pin PGND (18) be left unconnected to ground?

- pin VSS (36) is also left unconnected to ground or it is on potential (VCC - 3.3 V)?

- are SUB_GND(1) and for example SGND(27) on the same potential (different symbol)?

- can be pin VDDS (26) used instead of external 3.3 V regulator (IC2)?

- what is the bias voltage on pins INPA, INNA, INPB and INNB? Is this common voltage available on any pin (maybe SVR (29))?

[Peter BENSCH]

Welcome @iloveasic, to the community!

• PGND (18) should be connected only to the bypass capacitor and not to ground (internally connected)
• pin VSS (36) is an output (see table 1) and should be connected only to the bypass cap (see e.g. application circuits)
• SUB_GND(1) refers to the power stage side and the frame, SGND(27) refers to the signal (input) side. They are at the same potential, but you have to take the usual precautions (star-shaped merging at one point, see e.g. AN4015).
• VDDS (26) is switched off during STBY that's why an external 3.3V regulator (IC2) is necessary if STBY is used
• The input configuration of INPA, INNA, INPB and INNB can be seen in fig. 22 of the data sheet, the resulting potential results from the respective configuration and should be at about half the supply voltage of the opamps

Does it answer your questions?

Regards
/Peter