STM32 MPUs Products and hardware related

Hello,I am trying to understand this document:https://wiki.stmicroelectronics.cn/stm32mpu/wiki/How_to_deploy_SSP_using_a_step-by-step_approachGenerally speaking, I miss some context between the "SSP is nice to protect your firmware through HSM" and the how-to with many acronyms and missing explanations.I spend a couple of days reading related documentation and still feel very lost."2.2 Payload file"I understand this step as the creation of a file with all the secrets in it, including HSM and RMA keys/password.What are the meaning of RSSe, DHUK, BHK or DHUK_xor_BHK acronyms?** Question 1**  What are RSSe, DHUK, BHK ?2.2.1:My page looks very different. This section is not helpful.2.2.1.2:I believe this is the public key generated in step 2.1.1.What is the RMA password? I understand that this password allows to protect RMA mode, but how is it created? should I provide a file with a random 16 character password? or is this an AES key? Is it one of the private keys generated in step 2.

hello team I have designed a custom board based on the STM32MP157FAC1 and would like to request a review from experienced members to ensure its correctness and optimal performance. I have attached the schematic  for review.

Hello ST People !I'm looking for information / possiblity to use SPI (via spidev & ioctl) in Linux user space with DMA.We have to transfert lots of data (4000bytes at one time, very very often) to a fpga, very quickly and we are facing latency issue during transfert.With the help of a scope, we see dead times between spi transactions during this big packet write.So we are thinking using spi dma to unload cpu, but we need some infos/direction to look for.Maybe someone help or points me to right direction?Bon weekend!

Hi,at https://www.st.com/en/evaluation-tools/stm32mp257f-ev1.html# the CAD-data of the STM32MP257F-EV1 evaluation board are provided. This imports well into KiCAD, however nearly all footprint data are missing. For cpacitors and resistors with standard sizes this is easy to resolve but for several other components this is a big problem.The missing footprint libraries have names like C__VIRGIL_AAA__JOB_ALTIUM_STM_Library_Altium_Library_Altium_STM-LMS_MCD_PARTS.PcbLib:CON_MICROSD_ATOM_MR01A-01211So it seems, there is a STM Altium Library available somewhere, that contains these footprints.Since Google did not know anythign about this library, my question: where can get one this footprint library in order to import the board properly?Thanks! 

Hello, I built FIP artifacts following wiki, `STM32MPU Developer Package`, 5.2. Installing the OpenSTLinux BSP packages.And I could get binary files:1. TF-A binary: tf-a-stm32mp157d-smp4-mx-optee-emmc.stm322. OPTEE binary: tee-*.bin files3. u-boot binary: u-boot{,-nodtb,-dtb}.bin filesI did not build linux kernel yet. I want to check PMIC's 1.35v output in current step, because I've read somewhere in ST wiki that works when TF-A is flashed.But Cube Programmer disconnected from the device before doing something.  <-- This was soldering problem. after resoldering, its fixed.and even more, eMMC is not detected in cube programmer. 10:12:34 : UR connection mode is defined with the HWrst reset mode 10:12:35 : USB speed : High Speed (480MBit/s) 10:12:35 : Manuf. ID : STMicroelectronics 10:12:35 : Product ID : DFU in HS Mode @Device ID /0x500, @Revision ID /0x0000 10:12:35 : SN : 003B00413432510735313430 10:12:35 : DFU protocol: 1.1 10:12:35 : Board : -- 10:12:35 : Devic

Hi,I'm working with an STM32MP257-EV1, and security is managed by OP-TEE. I'm trying to dynamically modify PMIC voltages from a Linux module.I've read that the PMIC is managed by OP-TEE via the SCMI subsystem.I tried calling the Trusted App SCMI from the OP-TEE Client API, but I got an "access denied" error.Should I use the SCMI Client API directly or the Linux regulator API?Is it possible to get a code example of PMIC management from Linux via OP-TEE? I found a lot of explanations and diagrams, but I counldn't find any actual source code examples.Best regards,Jerome

HelloI have a cutom board based on STM32MP157D-EV1.The dts is based on stm32mp157f-ed1.dts with minor differences:* HSE: Bypass -> crystal (There is a 24MHz crystal). Removed "st,digbypass;" from &clk_hse* DDR: 32bit 8Gb -> 16bit 4Gb. (Using MT41K256M16TW-107). Change the included ddr.dtsi to #include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi" When flashing, I get this error: ERROR: DDR addr bus test: can't access memory @ 0xc0000004I can see that the 1.35V does never ouput from BUCK2 of the PMIC, so I assume that the origin of the issue is there. I have modified the tf-a code to add traces and can see that buck2 should indeed be enabled. The HW works: I have run another build based on kirkstone on the same HW. I am running out of ideas of where to look next. Does anyone have any ideas? The dts: Spoiler (Highlight to read)// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) /* * Copyright (C) STMicroelectronics 2022 - All Rights Reserved * Auth

Hello,We are researching the possibility to protect different pieces of our software on Linux (OpenSt-Linux) and firmware for the M33 on the STM32MP257.Our goals are (mostly) aligned with the purpose of the SSP HSM mechanisms:1) Avoid our firmware to be copied, either by the final client or by our (non-trusted) manufacturer.2) Ensure that no more than sold licenses are installed on HW (by the manufacturer).3) Ensure the firmware is a signed versionMy understanding is that this is basically the goal of SSP / HSM:* We setup an HSM card with licenses (counter) and keys.* We setup a secret file including keys.* The manufacturer use them to establish an USB connection with the STM32MP2, and save keys in the OTP, where the secret file (keys) is encrypted all the time until saved in the OTP, at which point it's not readable.* To make the OTP not readable, the MP2 is switched to OTP_Secured_Close using the RMA mode.With this, we would like the non-secure Linux to:1) Verify the signature of fil

Dear ST Rep,  The information within AN5489 regarding the pin-lengths for the high-speed serial interfaces of the MP2 (ie,. DSI / CSI / LVDS / and "COMBOPHY") potentially has some errors, or at the very least is unclear and I would greatly appreciate some help making sense of it.  Side note -  The raw pin-length data provided for the DDR interface is exactly what a designer wants/needs in a design.  I'm not sure why the same information for the other high-speed interfaces on the MP2 was converted as it was, but it's far less useful (imho).   If the raw pin length data could be provided for the above-mentioned interfaces - all my questions will be answered.   To that end - I struggle to make sense of the information regarding the trace length matching for high-speed interfaces (via AN5489), for the reasons stated below: Per Section 8.19: (pg. 78; Rev3)"Each package has been optimized to provide easier length matching when diffe

I am following the contents of STM32MPU Distribution Package in STM32 Wiki6. Building the OpenSTLinux distribution↑.When I build using the bitbake st-image-weston command, the following error occurs.ERROR: openssl-native-3.2.2-r0 do_compile: oe_runmake failedDoes anyone know about the above problem? (I'm using Ubuntu 22.04.)

Whether the part STM32MP131FAE7 can be reflowed twice or any solder requirements

When will this product be available in retail ?  The ECO system already supports this board but there is no STMICRO hardware, except the EV board. 

 [1] Why is the STM32MP257 called STM32 and not STM64 :) for 64 bit ?[2] What is the reason the board uses as display output LVDS instead of the 4 lane MIPI and/or RGB888 ?    

Hello Anyone can Help me to solve this Issue  I am using STM32MP257F-EV There is  a week ego try to troubleshoot this issues by installing all necessary drivers  but still not working , when I want to run the code via IDE it is showing busy and COM ports number, Any assistance please

I enabled CAN in the device tree using STM32CubeMX and followed the instructions in the provided documentation to generate the .dtb file. Afterward, I copied the generated .dtb file to the /boot directory. In the terminal, I ran the following commands: sync reboot After rebooting, I checked the dmesg log and found the following output when filtering for CAN-related messages: dmesg | grep can [ 0.451665] can: controller area network core [ 0.451819] can: raw protocol [ 0.451832] can: broadcast manager protocol [ 0.451847] can: netlink gateway - max_hops=1 However, when I checked the available network interfaces can0 isn't avaliable root@stm32mp1-e1-99-00:~# ls /sys/class/net end0 lo usb0 wlan0 I have attached the dts file for reference

Hi,I am designing a product based on the STM32MP157DAC specifically using the TFBGA257 package due to its compact size. I was just looking at the datasheet (page 16, Table 1) and noticed that under the SDRAM section it seems that this package doesn't support 32 bit. I have trawled the internet for additional information to support this but can't find anything that might suggest this to be the case. Can anyone chime in if you've had any experience using this package or if you know of any additional literature. Cheers,

Hi,i have a question to the memory-controller and the supported memory-size.I'm using the Part STM32MP157CAAx (Package: LFBGA448).In the Datasheet (STM32MP157C/F) and AN5031 there is a definition to the supported SDRAM size.For package "LFBGA448" the SDRAM is defined as following.- DDR3/3L (16bits 533MHz) up to 1Gbyte., single rank.My Questions:a.) Does the Memory-Controller support a DDR3L (Configuration 512Meg x 16) with "Single-rank and Twin-Die?b.) Does the Memory-Controller support the following Page sizes:     - Page-Size= 2KB     - Page-Size= 1KB (Page size per die)Could you please give us support, to answer the questions.Thank you.Reguards        

Hello, I am working on bringing up the STM32MP257F-EV1 board and running into a problem with the steps on the page: https://wiki.st.com/stm32mpu/wiki/Getting_started/STM32MP2_boards/STM32MP257x-EV1/Develop_on_Arm%C2%AE_Cortex%C2%AE-A35/Modify,_rebuild_and_reload_the_Linux%C2%AE_kernelSpecifically step 4 when it has you build the Kernel and the device tree.  When I run the command make ${IMAGE_KERNEL} vmlinux dtbs LOADADDR=0xC2000040 O="${OUTPUT_BUILD_DIR}" it goes through the make process fine and successfully builds the image but fails on the device tree. I get the following message when the build finishes:Kernel: arch/x86/boot/bzImage is ready (#1)make[1]: Nothing to be done for 'vmlinux'.make[1]: *** No rule to make target 'dtbs'. Stop.make[1]: Leaving directory I should probably note that I am using Ubuntu  22.04 and my architecture is x86_64. Any help would be greatly appreciated. Thanks! Carson

Hi,I am debugging STM32MP2 via JTAG and would like to access a process via DAP.  I believe it is possible via the Debug Domain CID (DDCID)that is mentioned in this URL:https://wiki.st.com/stm32mpu/wiki/Resource_Isolation_Framework_overview Unfortunately, I am unable to find proper documentation and steps involved.I would appreciate any advice regarding how to access a resource using DDCID.Thank you.Best regards,Aiyps

Is there a tutorial for newbie? I made my custom board by myself as hobby.the board has switches to select boot 0 and boot 1, boot 2 is tied to ground through 10k resistor. so I could implement boot selector that switches between `00` flashing mode, `01` serial NOR, `10` NAND, `11` eMMC on SDMMC2. and I tested the MPU could run as DFU mode and I could see it in Cube Programmer tool.but I can not get understood how can I flash linux to my board. exactly, I could build linux using yocto but, where should I put my DTS files that generated by Cube IDE?I'm under WSL2 environment to build yocto. unfortunately, I'm not expert of linux kernel :( 

Hi,I am looking to design a board based on a 64-bit ARM processor, with interfaces including USB, Serial, and Ethernet. Could you kindly suggest any development boards that could serve as a good reference for this project?Your recommendations would be greatly appreciated. Thank You

It seems that some of the ones my monitor is reporting ought to be within the range, but I'm only seeing Modeline 46:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 Whereas the following are rejected for various reasons - I can understand the CLOCK_HIGH ones, but not so much the CLOCK_RANGE ones - they appear to be lower than the dot-clock in the accepted modeling... [ 2622.968539] [drm:drm_mode_addfb2] [FB:36][ 2623.683425] [drm:drm_mode_addfb2] [FB:38][ 3167.141720] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:29:HDMI-A-1][ 3167.163438] [drm:drm_add_display_info] non_desktop set to 0[ 3167.163489] [drm:drm_add_edid_modes.part.19] ELD: no CEA Extension found[ 3167.163504] [drm:drm_add_display_info] non_desktop set to 0[ 3167.163774] [drm:drm_mode_debug_printmodeline] Modeline 37:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9[ 3167.163791] [drm:drm_mode_prune_invalid] Not using 1920x1080 mode: CLOCK_HIGH[ 3167.163814]

Hello,I use SDL with X11 for now but I want to use it directly with kms/drm kernel driver. I run basic_splash_drm and it works.I don't know how to configure sdl to work together with kms/drm, somebody use it in this way ?Regards,Adrian

Currently, I'm running the M4 core by loading it through the A7 core.Is there any way to make these two cores start independently, without interfering with each other, and only perform communication?

I understand that there would be great performance penalty for the combination of cortex A35 core with octospi psram, but I want to know if this is possible after all? Of course, without great effort on modification of u-boot and kernel code. Just bring up psram in uboot and hopefully cortex A will treat it as usual without significant difference than that of lpddr4. We have a custom-developed product that requires absolutely active state low current as well as PCIE and Linux (for multiple file system on HDD/SSD). Weird enough, may be mmu-less cortex M such as stm32h7 will do the job either, but, we don't trust linux on mmu-less processors. Cortex A will be much better in stability.