STM32 MPUs Products and hardware related

I'm very proud of STM32MP1 and I want to continue to learn more about the STM32MP products.So, I'm planning to create another single board computer such as the open source project STM32-Computer. My next project will be STM64-Computer, which will use STM32MP257.I have some questions that are refering to the STM32MP2 series.Can I surf on Youtube with that?Can I stream with that?Can I use regular programs such as Libre Office, Putty, Java, VS Code on that?Are there any limitations?How powerfull is the GPU? E.g can it do facial recognition?Is the setup, configuration, hard ware etc. almost the same as STM32MP1? I mean, if I have made a single board computer with STM32MP151, then a STM32MP257 will be exactly the same, just another more expensive and power full processor?Why is STM32MP257 so difficult to get? I can only see DigiKey have some few in stock.Is it possible to route the conductors on the PCB with 4 layers PCB, or do I need 6 layers or more for the STM32MP257? I know the getting

Hello, st:The board I have on my hand is stm32mp257f-ev1.Now I have a problem. The gstreamer cannot work properly when playing mp4 format video.Does the h264 decoder need to be activated or enabled?I run this commandgst-launch-1.0 playbin3 uri="file:///home/root/Videos/2002.mp4"here is the error:and also the gst-discovery-1.0root@stm32mp2-e3-c2-aa:~# gst-discoverer-1.0 Videos/2002.mp4 Analyzing file:///home/root/Videos/2002.mp4 Done discovering file:///home/root/Videos/2002.mp4 An error was encountered while discovering the file Failed to configure H264 decoderIt seems that I can play webm format video but not mp4.I tried the software decode avdec_h264, but it only has 15 fps.But in fact the h264 plugin has been installed on my board.root@stm32mp2-e3-c2-aa:~# gst-inspect-1.0 | grep h264 codectimestamper: h264timestamper: H.264 timestamper libav: avdec_h264: libav H.264 / AVC / MPEG-4 AVC / MPEG-4 part 10 decoder rtp: rtph264depay: RTP H264 depayloader rtp: rtph264pay: RTP H264 payloa

Hello,I am running on a stm32mp255dak processor with Linux running on the A35 core and FreeRTOS on the M33 core. I am running the M33 core code out of DDR.I am seeing an issue where the M33 core performance takes a hit and missed deadlines when the A35 core loads the DDR. The issue is very similar to the one described in this forum. https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1220944/am625-lpddr4-access-priority Does anyone know where to start looking to find the root cause of this issue? I done some investigation into the DDRCTRL registers and tired to mess if the QoS of the A35 core, but that did not seem to make a difference. It seems like the issue is a DDR contention issue between the two cores.

my code only made changes the io, no rtos, no interrupt, but it cost over 1 us.  the picture is that io sta. and clock

I'm investigating 2.5Gb Ethernet PHYs for our STM32MP257D board.  Most, if not all, require SGMII which is not explicitly supported in the ST MPU documentation.Anyone been down this road?Anyone know of a compatible 2.5Gb PHY that can use the STM32MP2xx RGMII?Thx

Hi,I’m having an issue with flashing OpenSTLinux Android (OpenST-Droid) on the STM32MP257F-EV1 board.I followed the instructions in the following document:STM32MPU Distribution Package for Android - stm32mpuHow to build OpenSTDroid distribution - stm32mpuHow to populate boards for Android - stm32mpu However, when I start the flashing process using STM32CubeProgrammer, it stops at 0x01 and does not proceed further.Could anyone help me understand what might be causing this issue, and how to resolve it? Thanks in advance!

I am running bitbake core-image-minimal;The build error is as followsERROR: mesa-2_24.0.7-r0 do_configure: meson failed ERROR: mesa-2_24.0.7-r0 do_configure: ExecutionError('/home/l/yocto/build/tmp-glibc/work/cortexa7t2hf-neon-vfpv4-oe-linux-gnueabi/mesa/24.0.7/temp/run.do_configure.1438955', 1, None, None) ERROR: Logfile of failure stored in: /home/l/yocto/build/tmp-glibc/work/cortexa7t2hf-neon-vfpv4-oe-linux-gnueabi/mesa/24.0.7/temp/log.do_configure.1438955 Log data follows: | DEBUG: Executing python function extend_recipe_sysroot | NOTE: Direct dependencies are ['/home/l/yocto/layers/openembedded-core/meta/recipes-core/expat/expat_2.6.2.bb:do_populate_sysroot', '/home/l/yocto/layers/openembedded-core/meta/recipes-core/glibc/glibc_2.39.bb:do_populate_sysroot', '/home/l/yocto/layers/openembedded-core/meta/recipes-core/zlib/zlib_1.3.1.bb:do_populate_sysroot', '/home/l/yocto/layers/openembedded-core/meta/recipes-devtools/gcc/gcc-cross_13.3.bb:do_populate_sysroot', '/home/l/yocto/layers/

Hi Everyone,I'm trying to understand the NOR Flash boot sequence of stm32mp257f-ev1. Im using generated FlashLayout_nor-sdcard_stm32mp257f-ev1-optee.tsv to flash the st-image-weston image.I want to understand how exactly the boot sequence is started and how it reaches to the u-boot (normal-world boot). I had a pre-work in understanding this boot sequence, I need a clarification on my understandingThe stm32mp2 boards follow arm trusted boot chain. That means TF-A and OPtee will be the FSBL and U-boot will be SSBL. So during the power on cycle the ROM code initiates the OCTOSPI interface of the Processor in Legacy SPI (MOSI and MISO) mode at HSI/2 = 32MHz speed. Then is loads the Initial DT + BL2(optee) to SRAM and initialise the CPU clock and DDR.Once the CPU is initialised, based on the arm-firmware SPI_NOR and SPI_MEM framework and the boot_device.c configuration, the OCTO SPI is configured to QUADSPI in 1-1-4 (QREAD) mode at max speed (133MHz) speed and

I'm working with the STM32MP257F-DK board and using the NXP IW612 wireless module, which is connected through the Murata uSD-M.2 adapter via the board's microSD card slot.When I connect the adapter, the mmc interface detects it in high-speed mode, with a clock frequency of 50 MHz and a signal voltage of 3.3 V.To cross-check, I connected a standard SD card to the same slot, and it was correctly detected in UHS mode with a 100 MHz clock and 1.8 V signal voltage.I want the Murata adapter (with IW612) to operate in UHS mode, using: A higher clock frequency (e.g., 100 MHz or above)1.8 V signaling (switch from default 3.3 V)What steps are required to achieve this? Do I need to modify the Device Tree(DTB)? Are any voltage regulators or GPIO controls required to enable the 1.8 V switch? What are the minimum hardware/software dependencies to ensure UHS mode is enabled for the SDIO interface used by the IW612?

Hello,My aim is to install OpenCV and use it's functionalities on STM32MP1 board. But I coulnd't find a proper documentation about it. Could you help me with this?Thanks.

I generated the M33 code using CubeIDE by following the lab manual.During the driver initializations:MX_ADC1_Init();MX_I2C1_Init();MX_ICACHE_Init();MX_RTC_Init();The A35 halts CPU1 and resets after sometime.E/TC:0 stm32_iac_itr:192 IAC exceptions [159:128]: 0x10000000E/TC:0 stm32_iac_itr:197 IAC exception ID: 156E/TC:0 Panic at /usr/src/debug/optee-os-stm32mp/4.0.0-stm32mp-r1/core/drivers/firewall/stm32_iac.c:212 <stm32_iac_itr>E/TC:0 TEE load address @ 0x82000000E/TC:0 Call stack:E/TC:0 0x82007ed8E/TC:0 0x82041b44E/TC:0 0x8202c2c0E/TC:0 0x8203f678E/TC:0 0x82013cf4E/TC:0 0x820017dcI/TC: Halting CPU 1Unfortunately I failed to create astable functional M33 for my MPU project yet. Are there no proper manual of code generation and configuration?

NOTICE: CPU: STM32MP135F Rev.YNOTICE: Model: STMicroelectronics STM32MP135F-DK STM32CubeMX board - openstlinux-6.1-yocto-mickledore-mp1-v23.06.21NOTICE: BL2: v2.8-stm32mp1-r1.0(release):custom()NOTICE: BL2: Built : 15:38:01, Jul 2 2025NOTICE: BL2: Booting BL32I/TC: Early console on UART#4I/TC:I/TC: Embedded DTB foundI/TC: OP-TEE version: Unknown_3.19 (gcc version 12.2.0 (Buildroot 2021.11-4428-g6b6741b)) #1 Wed Jul 2 06:15:25 UTC 2025 armI/TC: WARNING: This OP-TEE configuration might be insecure!I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.htmlI/TC: Primary CPU initializingI/TC: WARNING: All debug access are allowedI/TC: Platform stm32mp1: flavor PLATFORM_FLAVOR - DT stm32mp135f-dk-mx.dtsI/TC: DTB enables console (non-secure)▒_▒▒z`@`@▒▒ÿ▒▒▒▒▒▒▒▒▒▒▒zc`x@▒▒▒]▒▒▒▒▒▒▒▒▒▒▒@▒▒▒▒@▒▒▒@▒▒@▒▒▒▒▒z@xeeyybcb@\@▒▒▒▒@bac▒_▒▒z`@`@▒▒ÿ▒▒▒▒▒▒▒▒▒▒▒zc`x@▒▒▒]▒▒▒▒▒▒▒▒▒▒▒@▒▒▒▒@▒▒▒@▒▒@▒▒▒▒▒z@efdga`d@\@▒▒▒▒@a`c▒_▒▒z@▒▒▒▒▒▒▒@▒▒▒@▒▒▒▒▒▒▒▒▒@▒▒@▒▒▒▒▒▒@▒▒▒▒▒@▒▒▒▒

Hi everyone,I'm working with the STM32MP157C-DK2 board and trying to reduce the amount of RAM allocated to OP-TEE, but so far I haven't been successful.There are 32MiB DDR dedicated for OP-TEE. 30MiB for TZSRAM and 2MiB for SHMEM.In OP-TEE sources I changed value for CFG_TZDRAM_SIZE to 16 MiB and I'm keeping the value for SHMEM.In TF-a sources I changed value for DDR_SEC_SIZE to 16MiB.In Device tree I changed total RAM dedicated for OP-TEE to 18MiB.But when kernel start I have a fail: Starting kernel ... E/TC:0 E/TC:0 Core data-abort at address 0x2fff8762 (translation fault) E/TC:0 fsr 0x00000207 ttbr0 0x2ffe0000 ttbr1 0x00000000 cidr 0x0 E/TC:0 cpu #0 cpsr 0x600001f3 E/TC:0 r0 0x2fff8762 r4 0x2ffe1f71 r8 0x00000073 r12 0xe0000000 E/TC:0 r1 0x2ffe1f1c r5 0x00000000 r9 0x00000000 sp 0x2ffe1e70 E/TC:0 r2 0x2ffd3355 r6 0x00000000 r10 0x2fff8762 lr 0x2ffcdf77 E/TC:0 r3 0x2fff8762 r7 0x2ffe1f71 r11 0x2ffe1f58 pc 0x2ffcd8f8 E/TC:0 TEE load address @ 0x2ffc0000

I am able to use FDCAN1 to communicate on the A7 by adding the following to `STM32MPU-Ecosystem-v6.0.0/Developer-Package/stm32mp1-openstlinux-6.6-yocto-scarthgap-mpu-v24.11.06/sources/arm-ostl-linux-gnueabi/linux-stm32mp-6.6.48-stm32mp-r1-r0/linux-6.6.48/arch/arm/boot/dts/st/stm32mp157f-dk2.dts`:&m_can1 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&m_can1_pins_b>; pinctrl-1 = <&m_can1_sleep_pins_b>; clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>; status = "okay"; };  I'd like to allocate this can device to the M4 and use the example `STM32Cube_FW_MP1_V1.7.0/Projects/STM32MP157C-DK2/Examples/FDCAN`I need help is fixing this code to get a bitrate of 1Mbps and dbitrate of 2Mbps. static void MX_FDCAN1_Init(void) { /* USER CODE BEGIN FDCAN1_Init 0 */ /* USER CODE END FDCAN1_Init 0 */ /* USER CODE BEGIN FDCAN1_Init 1 */ /* USER CODE END FDCAN1_Init 1 */ hfdcan1.Instance = FDCAN1; hfdcan1.Init.FrameFormat = FDCAN_FRA

Hi STM Team,We are working with a custom board based on the STM32MP157DAC.We are facing a video lag issue when trying to play a video file from Qt application 6.5.3 using media player.Even reducing the frame rate had no effect.But if we use gst-play we are able to play the video without any lag or delay.Do we need to enable any HW accelerator to play the video over GPU from Qt application? how we achive the same video output without lag when played using gst-play from Qt application.Thanks.

Hello,I'm using Buildroot environment with the STM32MP257F-DK board. I'm testing GStreamer with a simple pipeline:gst-launch-1.0 videotestsrc ! autovideosinkWhen I first run it there is no problem. The test video shows fine on the HDMI monitor. But when I run it again second time there are errors : pipeline doesn't want to preroll. And all attempts after that fail too. It works only one time after the boot.There is additional debug info: drmModeSetPlane failed: No space left on device (28).Maybe some setting is missing ?BRraimo

I am using a custom board (STM32MP157DAA1) and want to use DSI 1 lane. How do I set it up in uboot or kernel?My screen also has 1 lane.

Hi !I am designing a SOM board (based on MP2 microprocessor) and I'm wondering if I must take into account the die-to-pin lengths on LPDDR4 IC side. Or does the intrisic architecture of LPDDR4 components garantee internal equivalent lengths ? I didn't find any related information on LPDDR4 IC manufacturer website, and there isn't much support.I've allready taken into account lengths on MP2 side.Thank you, have a nice dayBest regardsNicolas

We have a custom design based on STMP32MP133A na an spi NAND. On paper, using the u-boot diagnostic commands, everything is working correctly.NOTICE: CPU: STM32MP133A Rev.Y NOTICE: Model: Zehnder CCPRO A1R Board INFO: PMIC version = 0x21 INFO: Reset reason (0x35): INFO: Power-on Reset (rst_por) INFO: FCONF: Reading TB_FW firmware configuration file from: 0x2ffe0000 INFO: FCONF: Reading firmware configuration information for: stm32mp_io INFO: Using USB INFO: Instance 2 INFO: Boot used partition fsbl1 NOTICE: BL2: v2.6-stm32mp1-r2.1(debug):v2.6-dirty(a1f02f4f) NOTICE: BL2: Built : 13:14:26, Nov 23 2021 INFO: BL2: Doing platform setup INFO: RAM: DDR3-1066 bin F 1x2Gb 533MHz v1.53 INFO: Memory size = 0x10000000 (256 MB) INFO: DFU USB START... INFO: handle USB : Suspend int INFO: USB Suspend mode INFO: handle USB : Reset INFO: handle USB : Reset INFO: phase ID :3, Manifestation 0 at c716d456 INFO: Receive DFU Detach INFO: DFU USB STOP... INFO: BL2: Loading image id 1 INFO: Loading image id=

Heyho,I just checked the MCU selector in CubeMX (6.13), and to my surprise I didn't find any MPU supporting the following:gigabit ethernet (RGMII)FDCAN2 SAIs (I need at least 4 standard I2S/PCM "stereo" channels)The MP series don't have FDCAN.Then I checked the N6, but at least in CubeMX I was not able to configure RGMII with all 4 SAI blocks (1 SAI block as master, the 3 other blocks as sync slaves).That correct ?Thanks in advance! 

I need a partition as a backup partition for the root file system.How can I add a new partition in stm32mp2?

Hi,We are working on a custom carrier board based on STM32MP157DAC. We have built a custom yocto image.Yocto Version: MickledoreMachine: stm32mp15-discoSoM: STM32MP157DACDistro: openstlinux-westonLinux Kernel: 6.1.82-stm32mp-r2-r0WIFI-Bt: LBEE5PL2DL-921I have attached the dmesg log and device tree configuration.Is the driver support for this wifi-bt module directly available or do I need to configure something?bluetooth is configured as serial3 but I don't see any /dev/ttySTM2 device node.[ 14.597018] Bluetooth: Core ver 2.22[ 14.606728] Bluetooth: HCI device and connection manager initialized[ 14.614038] Bluetooth: HCI socket layer initialized[ 14.629270] Bluetooth: L2CAP socket layer initialized[ 14.637891] Bluetooth: SCO socket layer initialized[ 14.658379] Bluetooth: HCI UART driver ver 2.3[ 14.669248] Bluetooth: HCI UART protocol H4 registered[ 14.675392] Bluetooth: HCI UART protocol Broadcom registered[ 14.986555] Bluetooth: hci0: Frame reassembly failed (-84)[ 15.485933] Bluetoo

 Hi STM-Team, We have the custom board based on the STM32MP157DAC board.In that, we are not able to access the eMMC from u-boot command prompt. Currently, we are booting from SD card.We are able to see the 1 mmc device which is SD-card but not able to see any eMMC on device. Please see below logs: but emmc is being detected after kernel boot as seen from the dmesg logs and i was able to read and write to the emmc device  u-boot log:- STM32MP> mmc listSTM32 SD/MMC: 0 (SD)STM32MP>  dmesg log emmc being detected:- mmc1: new DDR MMC card at address 0001[    2.864763] mmcblk1: mmc1:0001 MT3204 3.56 GiB [    2.876500] mmcblk1boot0: mmc1:0001 MT3204 2.00 MiB [    2.884632] mmcblk1boot1: mmc1:0001 MT3204 2.00 MiB [    2.890880] mmcblk1rpmb: mmc1:0001 MT3204 512 KiB, chardev (244:0) below is my device tree configuration for sdmmc2 in kernel-source/arch/arm/boot/dts/stm32mp15x

Hi STM-Team,We have the custom board based on the STM32MP157DAC board with KLD35176BVIB LCD display.KLD35176BVIB is actually BOE3.49(VGA) + HX8394f  display.We are using yocto build to configure the display panel changes.I have attached my device tree configuration1) I need to configure below pins.Pin NamePin NumberFunctionImplementationRemarksPA14T2TP_INTTouch Panel interruptReference design has only DSI_LCD_INT, combined for Display + TPPD13AA19DSI_TEPin re-mapped FUNCTION MOVED FROM PC6 TO PD13PD15J2DSI_LCD_BL_CTRLPin re-mapped Function moved from PA15PH6Y11TP_RESET  I was not able to find how and where to map these pins for my display panel As I am not much familiar with ST pin-mapping I was not able to figure out these mappings.2) I was also looking for the DSI defaul data and clk pins pinmapping in device tree but not able to find it for below pins.DSI_D0PDSI_D0NDSI_D1PDSI_D1NDSI_CK_PDSI_CK_NDSI_RESETDSI_LCD_INT3) Additionally is there a display driv

Hi,We are using STM32mp157DAC som with a custom carrier board. We have built a custom yocto image. Yocto Version: Mickledore Machine: stm32mp15-disco SoM: STM32MP157DAC Distro: openstlinux-weston Linux Kernel: 6.1.82-stm32mp-r2-r0   below is my device tree configuration. aliases { serial4 = &usart1 }; &usart1 { pinctrl-names = "default", "sleep", "idle"; pinctrl-0 = <&usart1_pins_a>; pinctrl-1 = <&usart1_sleep_pins_a>; pinctrl-2 = <&usart1_idle_pins_a>; /delete-property/dmas; /delete-property/dma-names; status = "okay"; }; usart1_pins_a: usart1-0 { pins1 { pinmux = <STM32_PINMUX('Z', 6, AF7)>; /* USART1_Rx */ drive-push-pull; bias-disable; }; pins2 { pinmux = <STM32_PINMUX('Z', 7, AF7)>; /* USART1_TX */ drive-open-drain; bias-disable; }; }; usart1_idle_pins_a: usart1-idle-0 { pins { pinmux = <STM32_PINMUX('Z', 7, ANALOG)>, /* USART1_TX */ <STM32_PINMUX('Z', 6, ANALOG)>; /* USART1_RX */ }; }; usart1_sle