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Hello,first let me start this post by mentioning that I'm still very much a beginner.I'm writing my own abstraction layer functions for the N657X0.While running my clock_config() function, I ran into an issue that I don't know how to fix. The function works as follows:- reset RCC->CR, CRGR1, CFGR2- enable MSI and wait for MSI ready bit- set CPU & SYS clock source to MSI and wait for clock source confirmation bits- disable all other oscillators and all PLL- reset RCC->HSICFGR- configure HSI- enable HSI and wait for HSI ready bit- set CPU & SYS clock source to HSI and wait for clock source confirmation bits- disable MSI- reset RCC->MSICFGR- configure MSI- enable/disable oscillators (if HSIEN=0 then MSIEN=1 and vice-versa)- reset RCC->ICxCFGR- configure ICx- reset RCC->PLLxCFGRx- configure PLLx- enable PLLx and wait for PLLx lock ready bit- check CPU and SYS clock source selection- check if source is actually active by checking the corresponding ready bit again- sel

Hello, I'm trying to use TouchGFX. I created a new project and clicked on Generate code. Afterwards I get the following error message, which I do not know how to handle. Do you have any suggestions?Generate CodeCopy FrameworkCopying TouchGFX framework version 4.24.1 to C:\temp\testgfx\MyApplication\touchgfxDoneGenerateWrote config/gcc/app.mkWrote config/msvs/Application.propsWrote generated/gui_generated/include/gui_generated/common/FrontendApplicationBase.hppWrote generated/gui_generated/include/gui_generated/common/FrontendHeapBase.hppWrote generated/gui_generated/include/gui_generated/common/SimConstants.hppWrote generated/gui_generated/include/gui_generated/screen1_screen/Screen1ViewBase.hppWrote generated/gui_generated/src/common/FrontendApplicationBase.cppWrote generated/gui_generated/src/screen1_screen/Screen1ViewBase.cppWrote generated/simulator/gcc/MakefileWrote generated/simulator/include/simulator/mainBase.hppWrote generated/simulator/include/simulator/video/D

 Hi Partners,hope I can find you well through this mail,I need X-NUCLEO-IHM08M1 3D model(step), if you have the resource, please help me! thanks.  best regards,Crispian Liu 

Hi, I'm a bit stuck.   I'm trying to program watermarks for BANK2 (to make the entire bank secure so I can read the whole area using secure alias) for a custom boot-loader.   The code below is executing in secure context from BANK1 (and no bank swap).  It runs without error, but after a reset, the option bytes are still unchanged.   Im calling it with (FLASH_BANK_2, 0, 63, 0) as arguments. (63 being the last flash page of a 512KB bank - device is 1MB)   I am pretty sure I misunderstand something.   Kind Regards, Nick /**  * @brief Configures or Disables Secure Watermark for a specific bank.  * @PArambank: FLASH_BANK_1 or FLASH_BANK_2  * @PAramstart_page: Start page (Set > end_page to disable)  * @PAramend_page: End page  * @PAramlaunch: If SET, triggers a System Reset immediately to apply changes.  * @return true if the operation was successful, false otherwise  * @note to disable WM, set start_page > end_

Hello,I dug deeper into PSSI behavior, and and I observed unwanted behavior. From my point of view it is a bug.PSSI is configured as:OUTEN = 1 (transmit mode)CKPOL = 0 (outputs driven on rising edge, inputs sampled on falling edge)RDYPOL = 0 (0 at input indicates that the receiver is ready to receive)DEPOL = 0 (0 at output indicates that data is valid)DERDYCFG = 0b11 (Both PSSI_RDY and PSSI_DE alternate functions enabled)EDM = 0b00 (Interface captures 8-bit data on every parallel data clock)Chip STM32H7R3Z8T6, clocked at 600MHz from HSI, placed at PCB, powered by 3.3VPSSI kernel clocked by 150MHz and 300MHz (PLL from HSI)Transmitted data is rising numbers from 0 to 15, stored in array in AHBSRAM1, manualy written by core to PSSI->DR as 32bit values (four data bytes at one write). See source code:while (1){ if(PSSI->SR & PSSI_SR_RTT4B){ // wait until space in PSSI buffer PSSI->DR = arr[idxx]; // place data to buffer idxx++; // index to next data if(idxx >= BLOCK_SIZE

IntroWhen I'm using the "STM32CubeIDE for Visual Studio Code" extension, I often want to edit C source files outside of my workspace, which are listed in my CMakeLists.txt and get compiled into the firmware just like any other C file.  Unfortunately, with the default setup, the language server (clangd) cannot find some of the headers I include, and it doesn't know the right compilation options, so intelligent features like inlay hints (red squiqqlies) and the "Go to definition" command do not work properly.  The ST extension attempts to communicate this kind of information to the language server by putting a ".clangd" file at the root of my workspace folder which has a line in it like "CompilationDatabase: build_release".  But clangd won't consider that file when looking at source files outside of the workspace.MotivationI have multiple STM32 projects that share some common libraries, so my folder structure looks like:lib/lib1/lib1.clib/lib1/lib1.hlib/lib2/lib2.clib

Hello,I designed a custom PCB using the STM32F401RE (LQFP64), but I cannot connect to the MCU through SWD. I am using an ST-Link probe and the st-probe command-line tool.When I run the probe command, the ST-Link probe itself is detected, but the target MCU is not properly identified. The tool reports the flash size as 0x00.MCU: STM32F401REDebugger: ST-Link probeTool: st-probeObserved behavior:ST-Link probe is detected correctly.The MCU is not detected.Flash size reported as 0x00.Power measurements:VDD = 3.3 VVDDA = 3.3 V (through ferrite bead BLM18AG601SN1D)VCAP ≈ 1.2 V (2.2 µF capacitor connected directly, ~8 mm trace, no vias)NRST = 3.3 VTotal board current ≈ 18 mA (two LEDs also present)The MCU does not heat up, and current consumption appears normal.Power architecture:12 V input → buck converter → 5 V → LDO → 3.3 V (MCU supply)Analog supply filtering:VDD → ferrite bead → VDDADecoupling capacitors are placed near the MCU.Debug connections:SWDIO → PA13SWCLK → PA14NRST connected to th

I'm getting the "elf has a LOAD segment with RWX permissions" warning, and a quick search here reveals a couple of ways to get around this: Disable the warning, or edit the .ld file.However, in my case, I'm using the upper half of the STM32's flash area to emulate non-volatile memory.  So I want my flash to be writeable.Can anyone suggest some magic to put in my linker file that will make the warning go away, but also allow me to write to flash?Also: I'm using STM32CubeIDE, so my linker file is auto-generated.  Is there a user-override mechanism (like there is in the source code)?Thanks.

Title edited to state the issue being discussed.Really? After all these years? Padawan

Hi, I am seeking some guidance.With the new release STM32CubeIDE for Visual Studio Code 3.8.0, it says it comes with new features including " Serial terminal: Enabling developers to easily setup serial communication for example leveraging the ST-LINK virtual com port."In the docs, there is not much explanation on how to get this working. I only see:"If the serverPort attribute is defined, two ports are used by the ST-LINK GDB server: one for the debug session and serverPort + 1 for the SWO connection.These ports are reserved even if SWO is not activated in the debug configuration."How would one activate the SWO in the launch.json? I went through all the options with completition and none seem to activate or configure the SWO.I know that with the extension "Cortex-Debug" provided by marus25 we could configure the SWO as so:"swoConfig": { "enabled": true, "cpuFrequency": 275000000, // must match -a (Hz) :contentReference[oaicite:4]{index=4} "swoFrequency"

Hi, I'm trying to measure X-Nucleo-nfc03a1 with VNA: i got completely different values for C11 C22 and C2 as is on nucleo board. I understood something wrong? and when I remove Resistors 330ohm, inductor and 4 100pF capacitors I got like: 

Hello, I am experiencing a problem with ADC1 and ADC2. I configured them in Dual Regular Simultaneous Mode, where ADC1 acts as the master and ADC2 acts as the slave. The ADC channel connections are as follows: ADC1 Channel 1: 24V_Sense ADC1 Channel 2: 5V_Sense ADC2 Channel 14: IOut_Sense ADC2 Channel Vrefint: Internal reference voltage However, I noticed that IOut_Sense always has a value, while 24V_Sense is unstable and fluctuating. OUTPUT:V24:24011 mV | V5:3 mV | I:23653 mA V24:8807 mV | V5:3 mV | I:8675 mA V24:8726 mV | V5:1 mV | I:8675 mA V24:8844 mV | V5:3 mV | I:8675 mA V24:23767 mV | V5:1 mV | I:23528 mA V24:23853 mV | V5:0 mV | I:23590 mA V24:23727 mV | V5:0 mV | I:23435 mA V24:23968 mV | V5:0 mV | I:23481 mA V24:8832 mV | V5:3 mV | I:8675 mA V24:23541 mV | V5:0 mV | I:23388 mA uint32_t adc_dual_buffer[4]; int main(void) { HAL_Init(); SystemClock_Config(); MX_GPIO_Init(); MX_ADC1_Init(); MX_ADC2_Init(); MX_USART1_UART_Init(); MX_I2C1_Init();

Split from STM32CubeIDE version 2.1.0 won't generate IOC project file as this is a new question.Please keep to one question per thread.Thanks both Ghofrane GSOURI & Andrew Neil for pointers. Adopting the method shown in the presentation. I have selected a nucleo development board to create an STM32MX project. I have then created a STM32CubeIDE projecfrom the MX project. Having not written any code yet, I'm getting compilation errors but have no idea why? The errors are relating to files marked with a red x below: 

I'm trying to set up FSMC in muxed mode to read_write external NOR flash devices. Muxed pins goes through 2 8-bit latches 74HC574D.The problem is that currently i can barely read from external NOR and it's not accepting commands.Firstly HAL_NOR_Init(&hnor1, &Timing, NULL) returns HALL_ERR  since it fails to read CommandSet from NOR. It should read address 0x13 from CFI and get 0x02 or 0x01 as a result, but write commad makes no effect and as a result driver reads at 0x13 from memopry start.After analyzing what's going on on the FSMC bus I still cand fing any clues. Here is an example how it performs ReadID sequence, using standard HAL_NOR_ReadID Everything looks correct, 3 sequences 0x555 - >0xAA, 0x2AA -> 0x55 and 0x555 -> 0x90, but reading 0x00 and 0x01 right after returns data from NOR not the deviceID I've also tried bitbang mode with same pins and code below successfully reads deviceID. So after all it's not a witing problem, but maby timings or so

Hello,When generating a basic Bluetooth project for NUCLEO‑WBA55CG using STM32CubeMx 6.17 (and 6.16) with Cmake as the toolchain, the project compilation fails to a missing symbol during the link stage.Here is the error message:le_ctrl.c:(.text.HCI_READ_LOCAL_VERSION_INFORMATION+0x20): undefined reference to `ll_sys_get_brief_fw_version'After investigation, it turns out the issue is caused by the incorrect order of linked static BLE libraries in the generated CMake file "cmake/stm32cubemx/CMakeLists.txt". CubeMX places the Link Layer and BLE Stack libraries in an order that prevents the linker from resolving symbols correctly. Reordering the libraries fixes the issue.Here is the corrected order that resolves the error:# Project static libraries set(MX_LINK_LIBS :stm32wba_ble_stack_basic.a :WBA5_LinkLayer_BLE_Basic_lib.a STM32_Drivers ${TOOLCHAIN_LINK_LIBRARIES} Utilities STM32_WPAN Common ) Best regards

Hi Together,I am currently trying to use the FMAC hardware accelerator. Normal usage already works. Now for numerical stability I want to implement the filter as second order sections (sos). According to RM0481:Cascaded filters must either be combined into a single stage, or implemented asseparate filters. In the latter case, multiple sets of filter coefficients can be pre-loadedinto the memory, one set per stage, and only the X2_BASE address changed to selectwhich set is used.To do this I currently:Concatenate all the stage coeffs into one vector:static int16_t const b_Coeffs_0[b_Coeff_len_0] = { 55, 111, 55 }; static int16_t const a_Coeffs_0[a_Coeff_len_0] = { -3745, -258 }; static int16_t const b_Coeffs_1[b_Coeff_len_1] = { 16384, 32767, 16384 }; ...static int16_t all_coeffs[sos_Coeff_Count] = { b_Coeffs_0[0], b_Coeffs_0[1], b_Coeffs_0[2], a_Coeffs_0[0], ...On setup input the vector as b coefficients:filter_Config.Clip = FMAC_CLIP_ENABLED; filter_Config.Filter = FMAC_FUNC_IIR_DIRECT

Having some issues trying to debug a FreeRTOS project using JLink, using an STM32U5G9 (Riverdi 5" Display Board) If I enable "serverRtos" in the launch configuration:"configurations": [ { "type": "jlinkgdbtarget", "request": "launch", "name": "STM32Cube: STM32 Launch JLink GDB Server", "origin": "snippet", "cwd": "${workspaceFolder}", "preBuild": "${command:st-stm32-ide-debug-launch.build}", "runEntry": "main", "serverSpeed": "12000", "serverRtos": { "enabled": true, "port": "60000", "driver": "freertos", "driverPort": "ARM_CM33_NTZ" }, "preRunCommands": [ "monitor exec SetRTTSearchRanges 0x200bb800 0x234800" ], "imagesAndSymbols": [ { "imageFileName": "${command:st-stm32-ide-debug-launch.get-projects-binary-from-context1}" } ] } ]And then try to start a debug session, i get a disconnect error:Reading 20 bytes @ address 0x200C2A5C Read 4 bytes @ address 0x200C2A28 (Data = 0x200C2970) Read 4 bytes @ address 0x200C2A58 (Data = 0x200BEA20) Read 4 bytes @ add

Hi team,Can you please help me with the Single Event Effect (SEE) analysis, Type of technology used, Technology Feature Size details for LDCL015MR? 

Hello,I want to develop a LoRaWAN sensor with STM32WL5MOCHxS, but I can't activate the LSE and HSE clock in CubeMX.Is there a way to make the adjustments in the .ioc?The configuration is possible in STM32WL5MOCH (expired).

Hi everyone,I’m having an issue connecting my STM32N6570-DK board to STM32Cube.AI Studio.The board is detected correctly by my computer, and I can see the COM port in Windows Device Manager. However, when I open STM32Cube.AI Studio and go to Board Settings, the COM port list is empty, so I cannot select the board.Here is what I have already checked:The board is connected via USB and recognized by Windows.The COM port appears normally in Device Manager.I set the board to DEV mode with Switch 1 = HIGH.I restarted STM32Cube.AI Studio and reconnected the board.Despite this, the COM port does not appear in the Board Settings dropdown in STM32Cube.AI Studio.Has anyone encountered this issue before with the STM32N6570-DK or similar boards?Is there any additional configuration or driver required for STM32Cube.AI Studio to detect the COM port?Any help would be greatly appreciated. Thanks!Best regards.

There is a problem with saving assembler source files when the C/C++ > Editor > Save Action > Format source code option is enabled:As a result, the file is not saved, and when it is just created, there is no file at all. It's quite irritating, especially because this is quite an old bug and no one has resolved it yet.

I can't get the STLink drivers installed on Windows 10 / 11 aarch64 Parallels VM running on Mac M1.Is there any support for ARM64 Windows STLink drivers?

Hi guys, Recently I have started to do some practical test with STM8S105. While trying to implement  PWM of TIM1 CH1 and CH2 with their complementary channels, it is seen that PWM pulses are generated only on main channels. Complementary channels are silent. Please see the code and suggest the way out.   #include "stm8s.h" void setup_clock(void) { CLK->ICKR |= CLK_ICKR_HSIEN; // Enable HSI while (!(CLK->ICKR & CLK_ICKR_HSIRDY)); CLK->CKDIVR = 0x00; CLK->SWR = 0xE1; } void setup_gpio(void) { GPIOC->DDR |= (GPIO_PIN_1 | GPIO_PIN_2); GPIOC->CR1 |= (GPIO_PIN_1 | GPIO_PIN_2); GPIOC->CR2 |= (GPIO_PIN_1 | GPIO_PIN_2); GPIOB->DDR |= (GPIO_PIN_0 | GPIO_PIN_1); GPIOB->CR1 |= (GPIO_PIN_0 | GPIO_PIN_1); GPIOB->CR2 |= (GPIO_PIN_0 | GPIO_PIN_1); } void setup_tim1_complementary_pwm(void) { TIM1->CR1 &= ~TIM1_CR1_CEN; CLK_PeripheralClockConfig(CLK_PERIPHERAL_TIMER1, ENABLE); TIM1->PSCRH = 0x00; TIM1->PSCRL = 0x00;

Hello,I would like to confirm how VBUS behaves in STM32 USB OTG depending on the Host/Device mode.Specifically, I would like to ask the following:When STM32 is configured as Host mode, should the STM32 source 5 V onto VBUS?When STM32 is configured as Device mode, does it only sense/monitor VBUS as an input?Is this behavior handled automatically by the internal OTG controller, or does it require an external VBUS power switch or additional external circuitry?Additionally, I would like to ask about a hardware configuration where an external 5 V supply is always present on VBUS, regardless of the STM32 Host/Device configuration.In this case, I would like to confirm:Whether this could cause any issues when STM32 operates in Host modeWhether it could affect Host/Device role detection or OTG behaviorWhether USB enumeration and normal data communication would still function correctlyIn other words, I would like to know whether a design where VBUS is always supplied by an external 5 V source is

Issue Description:I am using the `STM32_Programmer_CLI` to flash the BLE Wireless Stack on an STM32WB series MCU. However, after the programming process is complete, the memory read returns an unexpected value at the Stack Version address, even though the GUI shows the correct version.**Steps to Reproduce:**1. **Read Initial "Stack Version":**```textReading 32-bit memory contentSize : 4 BytesAddress : 0x200100140x20010014 : 01180003```*(Note: 01180003 corresponds to Version 1.24.0.3)*2. **Delete "Stack FW"**3. **Read "Stack Version" again:**```textReading 32-bit memory contentSize : 4 BytesAddress : 0x200100140x20010014 : 00000000```4. **Flash "stm32wb5x_BLE_Stack_light_fw.bin"**5. **Read "Stack Version" after programming:**```textReading 32-bit memory contentSize : 4 BytesAddress : 0x200100140x20010014 : 130E0019```**The expected value is `01180003`.****Comparison with STM32CubeProgrammer GUI:**If I then switch to the GUI version of STM32CubeProgrammer:* **Connect** --> **Firmware