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Hi,I created a blank project for STM32U5G9J-DK2 and in process of programming the board, GfxDesigner generates 400MB file intflash.elf. With GfxDesigner 4.24.1 it is 4MB.Why 4.26.1 generates  intflash.elf so large ? A bug ?Thanks  

***Update***This issue is solved and was due to improper wifi firmware upgrade. Topic can be closed.   Hi STM Team, I have been having issues for the last week with connecting to the STWIN.box via wifi from both iphones and android phones for DATALOG2 v3.2.0. (And to some extent v3.1.0). The configuration of the wifi network does not work correctly when I attempt to send it from the app. The only way I could get it to work, is when I used the Python SDK with firmware version 3.1.0. I was able then to connect with FileZilla and view/download files.Please advise what the possible workarounds are with this issue as I need to use this sensor by connecting to it via wifi and downloading the data files via FTP server.The following is an AI-generated overview of the issue in more detail: Device: STEVAL-STWINBX1 (STM32U585AI) Firmware tested: FP-SNS-DATALOG2 v3.1.0 and v3.2.0 WiFi module: EMW3080 (firmware successfully upgraded per README instructions) App tested: ST B

I have a simple question. Is it possible to use TouchGFX+ThreadX with enabled Ethernet and NETXDuo SNTP client at a same time in STM32N6570-DK board? In other words: take the TouchGFX ClockExample then in CUBEMX enable the Ethernet port with NETXDuo-SNTP server. Will it cause pin conflict? I mean the Ethernet uses the same pins as LTDC. I enabled the Ethernet in ClockExample project and I got blank screen and the app was frozen. After removing Ethernet from the project, the analog and digital clocks appeared again on the display. Thanks, Louis

Good day,I am writing firmware for a custom board using the STM32G0B1KET6 and am experiencing issues related to writing a serial number to the internal flash.As far as I can tell, this MCU has 512 KB of flash split into 2 banks of 128 pages (each page is 2 KB). I am attempting to write to the last page of the first bank (Page 127 @ 0x803F800).I have modified the linker file to reduce the flash area used by my application code like so:MEMORY { RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 144K FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 64K }Here is my flash writing function. uint8_t Flash_Write(uint32_t startAddress, uint64_t data) { __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR); __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_BSY1); __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_BSY2); __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGSERR); __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGAERR); __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_CFGBSY); if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_CFGBSY) == 1) { return 0; } HAL_StatusTypeDef status;

Im trying to setup FreeRTOS with the new STM32N6.According to https://github.com/STMicroelectronics/x-cube-freertos, the new Nucleo board for the STM32N6 is mentioned as supported.But in the CubeIDE, when trying to enable the FreeRTOS middleware, it says that the new nucleo board is not supported. And the docs also only mention AzureRTOS as supported.Is FreeRTOS supported through the CubeIDE? Or only AzureRTOS? 

Hello,I recently came across an ST article describing a Condition-Based Monitoring architecture using a dual-MCU approach, with an STM32L476RG handling signal processing (and potentially edge AI), and an STM32WL dedicated to network connectivity.I find this architecture very interesting and relevant for a project I’m currently exploring, but I would like to better understand what level of support and resources are available from ST for implementing such a solution in practice.In particular, I have a few questions:Does ST provide official support or reference designs for this kind of dual-MCU architecture (STM32L4 + STM32WL)?Are there any example projects, application notes, or firmware packages that demonstrate communication between the two MCUs in this context?Regarding FUOTA (Firmware Update Over The Air), are there existing solutions or middleware provided by ST that support this setup, especially with STM32WL acting as the communication node?Are there recommended tools, libraries,

Newest AN4879 does not list STM32C5 as applicable products.

Hi everyone, I am trying to setup DCMIPP Pipe0 to read data from 256x192 pixel sensor by 16 data lines. Seems everything configured and working fine except of transfer data to destination buffer. DCMIPP frame counter is increasing. Pipe0 dump counter is 0x18000 (256x192x2). HAL_DCMIPP_PIPE_Start return HAL_OK. Pipe0 packer memory address register is qual to Pipe0 memory status address register and correspond to address of buffer in RAM. I checked that DCMIPP don't write zero values by initing frame buffer with 0xFF and it wasn't changed to zeros.   I am sure that sensor is working because of frame counter, dump counter, checking lines with oscilloscope and it is working with other pcb with STM32H7 and DCMI interface.   Also I validated that debugger read frame buffer correctly by sending it thought uart.   Source code is simple, generated by cube init than I2C configuration of sensor(validated) and than reading in loop with delay: while (1) { H

Hi Team, I am designing a custom PCB using STM32H753 and planning to use the QUADSPI peripheral for external memory. My use case is data read/write (indirect mode) — not XIP or memory-mapped execution. While working in STM32CubeMX, I came across some configurations that are confusing, and I’d like to clarify the actual hardware behavior. 1. Dual Bank vs Chip Select behavior In CubeMX, I can configure: QuadSPI Mode: Dual Bank with Quad Lines Chip Select options: Enable Chip Select 1 for both banks Enable Chip Select 2 for both banks Enable Chip Select for each bank My understanding: NCS → Bank1 NCS2 → Bank2 Questions: If I select “Enable Chip Select 1 for both banks”, does this mean: Only one physical flash is used and banks are logical partitions? Or is there any way two physical memories are still utilized? What is the exact meaning of “bank” in this context (hardware vs logical)? 2. BK1_IOx and BK2_IOx pins confusion CubeMX exposes: QUADSPI_BK1_IO0

I have recently installed STM32CubeIDE 2.1.1 on linux and opened an existing project workspace. Everything looks fine except the integration with CubeMX for ioc files (which I believe is now by-design). The problem I have is after going to eclipse marketplace and installing Subclipse, it installs fine, then after restarting it goes into an endless loop saying the application is not responding. Finally, I got a message about "Failed to load JavaHL Library.", but I'm not sure if that's the real cause as dismissing the dialog reverts back to the application not responding loop.  Reinstalling the IDE does not help. The only way I've found to get the IDE to work is by removing the stm32 folder under $HOME/.eclipse, but this doesn't correct the issue with subclipse or its connection to subversion. Any help much appreciated.

My device is quite power-sensitive. If I use a single DDR3L module with an STM32MP157 or 135, can I eliminate the need for a VTT power supply?

Hello,I'm trying to implement the Key Establishment workflow on my hardware based on STM32U5 MCU and STSAFE-A110 secure chip. The ephemeral key pair generation (StSafeA_GenerateKeyPair) works fine and the establishing key (StSafeA_EstablishKey) with the ephemeral private key and the remote host public key gives me a 48-byte shared secret by using NIST P-256 as curve ID.In the ST library provided, it is mentioned that the StSafeA_EstablishKey function provides a shared secret. In cryptography, a key agreement should return a shared secret on 32 bytes for NIST P-256 curve ID and then this shared secret may be used to compute a 48-byte shared key using HKDF with SHA-256 for example by providing salt and info.So what does exactly return the StSafeA_EstablishKey function of library? A shared secret or a shared key?Remote-side (Linux-OS computer), if I compute a key agreement using the remote private key and the STSAFE ephemeral public key, I get a 32-bytes shared secret (with

Can you increase the delay between Start and end frame packets.I want to make sure there's enough time for it to be detected with the STM32N6. Registers i've tried to use.  * VSYNC_START_DELAY - is for gpio output* FSYNC_IN_DELAY - not sure what it does  VD56G3 cam End frame packet.  

Hello, We are looking for suitable drivers for L9396. Got only the Datasheet & a WSS Operation document. Can you help with the SPI Driver ?   Regards, Prakash B J

Hi,I am working with the STM32N6 series MCU on the STM32N6570-DK board and have encountered a pin multiplexing conflict.As per the schematics and datasheet:PA15 (JTDI) and PB4 (JNRST) are multiplexed with LTDC signalsThese pins do not appear to have alternate mappingsMy use case requires:LTDC for driving the displayJTAG for debugging (full JTAG, not just SWD)However, enabling LTDC conflicts with the JTAG interface, specifically JTDI.I have a few questions:Is there any supported way to use both LTDC and full JTAG simultaneously on STM32N6?Are there any alternate pin mappings or remap options available that are not obvious from CubeMX?Is dynamic switching (e.g., using JTAG during debug and reconfiguring pins for LTDC at runtime) a viable or recommended approach?Are there any hardware workarounds or recommended debug strategies for this scenario?I understand that switching to SWD avoids this issue, but I would like to confirm if full JTAG usage is fundamentally incompatible with LTDC on t

Hello,I found a CubeMX database issue affecting STM32H747 dual-core projects using FreeRTOS with CMSIS-RTOS V2.EnvironmentMCU: STM32H747Cube/HAL: STM32CubeH7 1.13.xCubeMX: 6.17FreeRTOS: 10.6.2ProblemTwo FreeRTOS configuration parameters are not present in the MicroXplorer Configuration settings and are not retained in the internal IOC model:configUSE_SB_COMPLETED_CALLBACK configUSE_MINI_LIST_ITEMBecause of that, code generation can produce invalid output in FreeRTOSConfig.h such as:#define configUSE_MINI_LIST_ITEM ( valueNotSetted ) #define configUSE_SB_COMPLETED_CALLBACK ( valueNotSetted )This breaks the build and/or downstream FreeRTOS code.Editing the .ioc manually does not solve it permanently, because CubeMX overwrites the .ioc on regeneration.Adding manual defines in USER CODE blocks is only a local workaround and does not fix the root cause.Root cause foundThe issue appears to be in the CubeMX FreeRTOS mode database, not in the generated project itself.For STM32H747, CubeMX uses

Hi,Can I get the IBIS model of 54ACT157 2 input Mux IC?

Hello ST,What is the maximum current draw into the STM32H563/573's VDDUSB pin, please? Is this the same as IDD(USBBCD), i.e. 300 uA (ds14258 rev.6 Table 120)?

Hello,I tried to install the STM32CubeMX2 on Linux Lite 6.6 which is base on Ubuntu 22.04, but get unsupport file error.I double check that I allow this file to run as a program. Is there any guide on how to install it on Linux? Thank you. 

Hi, please share CMRT (Conflict Minerals Reporting Template) EXCEL FILE FOR STM32F051K8T7

H563ZI Nucleo and Nucleo-67W61. Using the CLI Binary version 1.1.0 I get: #### Welcome to ST67W6X CLI Application ###### build: 20:14:53 Sep 25 2025--------------- Host info ---------------Host FW Version: 1.1.0[ERROR] [575] [spi_xfer_engine] (spi_iface.c:297) Invalid magic 0x5501[ERROR] [575] [spi_xfer_engine] (spi_iface.c:512) Invalid spi header from peer, magic 0x5501, len (0, 0x0), version 0, type 0flags 0x0, rsvd 0x1[ERROR] [2575] [spi_xfer_engine] (spi_iface.c:448) waiting for spi txn ready timeouted[ERROR] [4000] [ST67W6XTask] (w61_at_common.c:375) sem_if_ready not received[ERROR] [4000] [ST67W6XTask] (w61_at_sys.c:314) Could not init Modem handler[ERROR] [4000] [ST67W6XTask] (main_app.c:783) [ERROR] in W6X_Init API[ERROR] [4000] [ST67W6XTask] (w6x_sys.c:101) W61 Init failed[ERROR] [4000] [ST67W6XTask] (main_app.c:283) failed to initialize ST67W6X Driver, 2##### Application end Suggestions? Thank you.

Hello guys, I would like to know if it is possible to directly connect  NUCLEO-F446RE board with  steval-mic003v1 mic array without any expansion board. Would love to know your feedback and much appreciated.

I am using a G474RE nucleo board and i have 2 separate interface boards which i ca connect to it. One board requires a VREFBUS of 2.5V and the other  2.90 . Currently i modify the .IOC file and select the appropriate VREFBUS, compile the code. So currently i have 2 separate .elf files, one for each scenario. I will want a single code version so that on start up based on the status of a switch connected to a GPIO, it will configure the correct VREFBUF value. The attachment shows my setup for the 2.90V internal voltage reference. Thanks David  

STM32L052TIM21, Channel 1: Output PWMTIM21, Channel 2: Switching between Output PWM and Input CompareSystem Clock: 32 MHzHello,I want to use TIM21 of STM32L052 for PWM output on channel 1 and input capture on channel 2 simultaneously. uint16_t TIM_CCMR1_backup; uint16_t TIM_CCER_backup; // PWM on channel 1 and channel 2 void PWM_init(void) { RCC->APB2ENR |= RCC_APB2ENR_TIM21EN; TIM21->CR1 &= ~TIM_CR1_CEN; TIM21->ARR = 0xFFF; TIM21->CR1 = TIM_CR1_ARPE; // TIM21, channel 1 TIM21->CCMR1 |= (0b111 << TIM_CCMR1_OC1M_Pos); // PWM mode 2 TIM21->CCMR1 |= TIM_CCMR1_OC1PE; // output compare preload enable TIM21->CCR1 = 0; // reset output compare register TIM21->CCER |= TIM_CCER_CC1E; // enable output // TIM21, channel 2 TIM21->CCMR1 |= (0b111 << TIM_CCMR1_OC2M_Pos); // PWM mode 2 TIM21->CCMR1 |= TIM_CCMR1_OC2PE; // output compare preload enable TIM21->CCR2 = 0; // reset output compare register TIM21->CCER |= TIM_CC

Hello! I'm attempting to build a custom bootloader for the STM32MP133C, heavily reliant upon the STM32MP13XX hal layer and then provided cmsis_core and cmsis_device_mp13 packages/pieces. I'm attempting this on IAR (company decision) which has added some wrinkles to this. I load the main application to the NAND flash using a custom flashloader, and then run the Bootloader code from sysram. Can't do both at the same time because IAR's flash loader uses the sysram.The bootloader initializes the necessary items- the HAL, system clock, DDR, UART, Flash, Ethernet, etc. I have it blink an LED 5 times for fun, and then load the .bin file from flash into a specific offset in the DDR, where I'm hoping to run from. I then set a function pointer to the starting location of the main app, and run that function pointer. It looks pretty simple/straightforward, as shown below:  GetApplicationDetails(flash); //loads from flash to DDR. void (*p_AppEntryPoint)(void);//boot the full OSp