uPSD 3254

[dshah08]

Posted on December 02, 2004 at 09:58

uPSD 3254

[dshah08]

Posted on May 17, 2011 at 12:03

I need to connect 32k SRAM to external address bus. The high order address bits 12-15 can be mapped to portB.

1. Where and how would I map this SRAM? 2. uPSD 3254 has its own 32K SRAM. Where is that mapped ? 3. Where are the uPSD 3254 mapped to ? 4. out of 64 K address space in Data area the upper 8000-FFFF area is used by Flash with 8 pages to make 256K Flash. 5. Do we use the lower 32k data area for SRAM ? :-)

[jdaniel]

Posted on May 17, 2011 at 12:03

Dilip,

It sounds like you need to familiarize yourself a little more with the 8051 architecture in general. The 8051 (and the uPSD3254) use separate memory spaces for code and again. Thus, you can have 64kB of data memory (SRAM) AS WELL AS 64kB of code (Flash) memory. ST allows you to control these separate busses and switch them around and even combine them if you like (via the VM register), but if you're doing something simple, you can just leave them separater. So... you can map internal SRAM to the lower 32kB of address space 0x0000-0x7FFF and external SRAM to the upper 32kB of address space 0x8000-0xFFFF. Then, using PSDSoft express, you can define a chip select for the external chip and set it to be active over that upper 32kB range. Or, of course, you can do it the down and dirty way and just tie A15 to the chip select. I'd recommend doing with PSDSoft and a DPLD chip select because then you can move the location of it around later. As far as paging the flash is concerned, the only important thing to realize is that the easiest way to do this is to only page out the upper 32kB of code space and keep the lower 32kB common. Otherwise various emulators and compilers/linkers will not work very well. Hope that helps.

[dshah08]

Posted on May 17, 2011 at 12:03

Hi,

I understand the division of 64K of code space and 64K of data space. The matter that requires clarity is for uPSD3254 1. I want to use 256K Main flash and want to be able to swith on the fly between code space and data spacewhich uses 8 page register outputs. 2. I also want to use 64K of SRAM external to the chip. If I wanted to create chip selects could I use the page register bits? I am mapping SRAM at 8000 to FFFF in data space. 3. If I were to decode 4 page register bits to create 16 pages can I use 8 for Main flash and 2 for SRAM ? :-)

[jdaniel]

Posted on May 17, 2011 at 12:03

Dilip,

All these things you're trying to do are possible, but the odds of getting the compiler to understand them is pretty slim. I'll try to detail each one: 1. You can certainly define 8 separate pages of flash memory. The only caveat is that you generally want to have a common block that's present on every page. So, for instance, you could map secondary flash from 0x0000 - 0x7FFF on every page and then have a different block of main flash mapped from 0x8000 - 0xFFFF on each of the first 8 pages. This would allow you to access all the areas. If you want to map it as ''data memory'' for a time, you would use the VM register, and this will ONLY work if you set the VM register to NOT access the upper 32kB of SRAM that you say you want to map. This will require more care than you can probably achieve easily with a compiler, because every routine that accesses this upper block of flash as data memory will need to NOT use any variables that are normally stored in SRAM. Also, you'll have to do the paging manuall unless you're using an advanced linker like Keil's LX51 which will allow you to define a far pointer (pointer to a memory address on another page). 2. You can certainly page the upper 32kB of SRAM. Again, though, you won't be able to use it for normal variable definitions unless you're using far pointers, etc. etc. What you would do is define some pins on the uPSD as chip selects and then set their memory range to 0x8000 - 0xFFFF. Next, you'd have to include in the ''product term'' for each chip select a page register bit. For instance, you could have the first one include (pgr7) and the other (!pgr7). If we continued with your example from above, this would mean that on pages 0 - 8, you'd have the first bank of SRAM and each of the pages of main flash, and then on pages 128 - 136 you'd have the second bank of SRAM, etc. 3. Yes, you can do that. If you're handling it all manually, however, you might just define some GPIO pins and use them as chip selects rather than worrying about the deode PLD since that's going to make your code paging more difficult. Somehow I suspect I'm probably making this more confusing for you, so I'll end there. :)

[dshah08]

Posted on May 17, 2011 at 12:03

Thank you phaze426. This is what I perceived see if you agree.

1. Assign Main Flash to 8 pages (8000 to FFFF)which can be in the code area or Data area depending on Vm register bits. If I want to write to the main flash I would jump to the data space. 2. Assign Secondary Flash to Lower 32k (0000 to 7FFF) of the code area common to all pages of Main Flash(No Paging) 3. The internal 32k ram is selected by Rs0 and resides in 0000 to 7FFF address space 4 The external off the chip 64K external ram can be selected by GPIO pins used as chip selects(These would be low true chip selects) residing in the 8000 to FFFF. Would this in any way conflict with the main Flash in the data area ? Since by default page0 of the Main Flash might be selected. :-)

[jdaniel]

Posted on May 17, 2011 at 12:03

Dilip,

I think you've just about got everything down now. The only remaining issue, I guess, is the problem you mention in part 4. Assuming everything is structured correctly, this shouldn't be a problem. Normally, when main flash is mapped into the upper 32kB of memory, the VM register should be set to only allow PSEN to access this (that is, it should be treated as code space). Thus, the only thing in the upper 32kB of DATA space is the block of external flash you select. The difficulty only comes in if you need to access external SRAM AND map the flash to the data area. Of course, you should really only need to map the flash to the data area if you're reprogramming it or something of the sort and as such you should be able to make sure you don't run into this problem. If you don't want to handle all of this manually, you could make the chip selects for these external flash blocks be DPLD outputs and then just setup different pages to map different combinations of flash/internal ram/external ram into different configurations. Any way you do it, it's all going to be a bit difficult to keep straight while you're writing your code. Good luck.

[dshah08]

Posted on May 17, 2011 at 12:03

One more question

1. If you use 4 bits of page register to create 16 pages can you have 8 pages of Main Flash in code space and use 2 pages of remaing pages in the data space for external off the chip SRAM ? Since I will be switching main Flash between data and code space. :-)

[dshah08]

Posted on May 17, 2011 at 12:03

Thank you phaze426. I think I understand what you are saying.

1. If I take 4 bits of page rgister bits I can create 16 pages and that can create exclusive chip selects for every combination of flash and external SRAM in the data area(8000 to FFFF). 2. If I use the previous idea of creating a chip select from GPIO for external SRAM in the data area 8000 to FFFF then make sure that Main flash and external ram are not selected at the same time in the data space. Does that sound right ? :-)

[jdaniel]

Posted on May 17, 2011 at 12:03

Sounds like you've got it.