STM32F334 How to deal with multiples ADC triggers?

[Asantos]

Posted on September 15, 2014 at 17:26

Hi,

STM32F334 has a great HRTIM capable of driving up to 5 half bridge converters, but it has only 2 ADC that share the same interrupt, how to trigger the ADCs in 5 different points?Ari

[Montassar BEN ROMDHANE_O]

Posted on October 02, 2014 at 10:29

Hi Ari,

Could you provide a little more information about the issue you?re experiencing?  By the way, the ADC1/ADC2 can be triggered by the HRTIM, please find below the table taken from reference Manual:Regards,Heisenberg.

[Asantos]

Posted on October 02, 2014 at 19:24

Heisenberg,

  The problem is not the trigger capability of the ADCs, the problem is that the two ADC share a single interrupt vector. My application need to implement one boost and two bucks converters, so I need 3 interrupts, one for each control loop. Has ST plans for a chip with HRTIM and four ADCs? Ari.

[Vincent Onde]

Posted on March 18, 2015 at 10:49

Hello Ari,

The STM32 ADCs have each 2 independent sequencers: the injected sequencer (register-based storage) and the regular sequencer (DMA-based storage), the injected having priority over the regular in case of trigger collision. Practically, in case of collision, the worst case conversion latency for a regular channel will be 400ns (2 conversions at  5MSps), considering a single injected conversion at once. The 2 ADCs can therefore control up to 4 independent converters, unless there are extremely precise sampling constraints for all of them.

The ADC discontinuous mode is another option to gather multiple sampling points within the same sequence. It is suitable whenever the order of ADC triggers is known and repeatable and there are no collision risks (sampling points must be at least 200ns away from each other). A typical use case will be for sampling voltage and currents in multiphase buck converter.

For what regards interrupts, a possibility is to use the end of (injected or regular) sequence interrupt for the ADC, the CPU only having to discriminate which of the sequencer issued the request (1 out of 2 flags). Another option is to use the timing units interrupt vectors (one for each unit). There are multiple interrupt sources available (one per compare register plus update and repetition events.

Bottom-line, if the 3 converters you’re mentioning are completely asynchronous, and one of them can afford a (slightly) delayed conversion trigger, the STM32F334 is perfectly suitable. Even better, if 2 out of the three converters are synchronous, the STM32F334’s ADCs should allow to place the sampling points at any place without any constraints.

I hope this helps,

Best regards,

Vincent