RM0367 (STM32L0x3) discrepancies

[waclawek.jan]

Posted on January 10, 2017 at 06:53

&sharp1

RM0367 Rev.5, Ch. 6.1.6  Dynamic voltage scaling configuration requires to

Poll VOSF bit of in PWR_CSR. ait until it is reset to 0.

twice. The note at the end of the same chapter says,

During voltage scaling configuration, the system clock is stopped until the regulator is

stabilized (VOSF=0).

Now how could (and why should) the processor poll for VOSF if it's effectively stopped?

JW

#wtf

[waclawek.jan]

Posted on January 10, 2017 at 07:01

#2

The description of the VOSF bit in 6.4.2  PWR power control/status register (PWR_CSR) says:

This bit is reset when VOS[1:0] in PWR_CR register change.

It is set once the regulator is ready.

and just below these lines:

0: Regulator is ready in the selected voltage range

1: Regulator voltage output is changing to the required VOS level.

So is it reset (which IMO means zeroed) after VOS changes, or set to 1?

JW

[waclawek.jan]

Posted on January 10, 2017 at 07:11

#3

In 7.3.1  Clock control register (RCC_CR), Bit 2 HSI16RDYF description says:

 This bit is set to ‘1’ only if the HSI 16 MHz oscillator is enabled by HSI16KERON or by IP request.

I have set RCC_CR.HSI16ON which IMO is not any of 'enabled by HSI16KERON or by IP request' and then RCC_CR.HSI16RDYF read as 1.

Why?

[waclawek.jan]

Posted on January 10, 2017 at 07:14

#4

In 7.3.1  Clock control register (RCC_CR), Bit 2 HSI16RDYF description, please specify what exactly means  or by IP request (list related IPs which can request HSI16ON, and/or link to related chapters where such request is described).

[waclawek.jan]

Posted on January 10, 2017 at 07:19

#5

In 7.3.1  Clock control register (RCC_CR), Bit 1 HSI16KERON description says:

High-speed internal clock enable bit for some IP kernels

but the text below appears to indicate that if RCC_CR.HSI16KERON is set, HSI16 stays on in STOP mode unconditionally, i.e. regardless of any IP being on or not. If this is really the case, I would remove any mentions of 'IP kernels' to avoid confusion.

[waclawek.jan]

Posted on January 10, 2017 at 07:46

#6

In A.8.1 Calibration code example, ADC_CR.ADEN is checked prior calibration and if on, it is attempted to be switched off by clearing it. But according to the RM, it can't be cleared directly and ADC_CR.ADDIS has to be used for this purpose.

This is similar to what is in

https://community.st.com/0D50X00009XkaBBSAZ

.

I did not check the L0Snippets.

[waclawek.jan]

Posted on January 10, 2017 at 08:18

#7

In 14.4.5  Configuring the ADC, first, proper treatment of ADCAL, ADEN, ADSTART and ADDIS bits in ADC_CR is described, then this section follows:

For all the other control bits in the ADC_IER, ADC_CFGRi, ADC_SMPR, ADC_TR,

ADC_CHSELR and ADC_CCR registers, software must only write to the configurationcontrol bits if the ADC is enabled (ADEN = 1) and if there is no conversion ongoing(ADSTART = 0).

However, for several items in the registers' description (e.g. ADC_CFGR1.RES, ADC_CFGR2.CKMODE, ADC_CCR.PRESC) it is explicitly prescribed that they must not be changed unless ADEN = 0 (and possibly other conditions apply). In fact, in the registers' description the only item requiring ADEN = 1 is ADC_CALFACT.

Please clarify.

[waclawek.jan]

Posted on January 10, 2017 at 08:41

#8

 

I suggest to add a comment after Calibration software procedure in 14.4.2  Calibration (ADCAL), explaining that ADCAL can remain to be set for some time even after EOCAL has been set, and that that may prevent subsequent setting of ADEN (or other related 'trigger' bits).

JW

[Igor Cesko]

Posted on January 10, 2017 at 13:54

This is mistake in Reference manual. Correct is:

This bit is set when VOS[1:0] in PWR_CR register change.

It is reset once the regulator is ready.

So practically is VOSF read always as zero.

[Igor Cesko]

Posted on January 10, 2017 at 15:08

This is mistake in Reference manual. It should be written in a more clear way.

Correct description is in the Chapter '7.2.2 HSI16 clock':

The HSI16RDY flag in the RCC_CR register indicates whether the HSI16 oscillator is stable

or not. At startup, the HSI16 RC output clock is not released until this bit is set by hardware.