Posted on April 23, 2013 at 14:17I found more or less graceful workaround and want to share it.
I reconnected memory WR pin from FSMC_NWE to FSMC_NL(NADV) and configured memory type as NOR flash and mode 2 (see p.31.5.4/''Mode 2/B - NOR Flash'' of reference manual). Now it's possible to tweak requred hold time with DATAST ! It also solves similar address hold issue !
But it's not guaranteed that reading will work with any memory, because I'm not sure whether it's correct logic when WR strobe toggles high during active RD. Also you can't read in fsmc modes with OE toggling because you may get unwanted write access (and collision on databus) just before NOE goes low.
If reading isn't working in your case and performance isn't critical for read accesses then you may try possible workarounds:
1. dynamically reconfigure memory bank to SRAM type before read access and return back when reading complete
2. dynamically reconfigure FSMC_NL pin to GPIO and set it high before read access and also return back at end.
But be warned, that FSMC is not strictly synchronous with CPU. Previous write access may be incomplete at the moment when you prepare read access, so insert required delay before that (maybe it's not required in first case, but I'm not sure whether it's possible to change fsmc configuration on the fly). I didn't tried these workarounds because it's not required in my case.
I'm interfacing FSA506 LCD controller. Both writing and reading works perfectly for me. (STM32F207IG, HCLK =120 MHz, FSMC_BCRx = 0x00001048, FSMC_BTRx = 0x00000A0A, FSMC_BWTRx = 0x0FFFFFFF)
(Note: datasheet says that maximum time between NADV low-to-high strobe and data setup is Thclk+2 ns, so it may not work in case if memory data latching isn't slow enough.)
