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While looking at STM32U3C5 and STM32H503 datasheets I found incorrect information on ICACHE. Quote:Hit ratio improved by two-ways set-associative architecture and pLRU-treplacement policy (pseudo-least-recently-used, based on binary tree), algorithmwith best complexity/performance balance The problem is: pseudoLRU may only be applied to 3- (or more) way set-associative caches. With 2-way set-associative, the single flip-flop per set provides true LRU and there is no such thing like “pseudoLRU” for 2 ways. You can’t do binary tree with a single flip-flop.  PseudoLRU is normally used with 4 or more ways, since for 4 ways pseudoLRU requires 3 flip-flops organized as 2-level tree, with simple state transition logic while true LRU - 4 flip-flops and 12 states with much more complex state transition logic.I suspect the same error might be present in all the STM32 documents describing MCU caches which are 2-way set-associative.

I am using the ST67W611M1A6UTR Wi-Fi NCP with an STM32H563ZIT6 MCU on a custom board.The ST67W611 is flashed with st67w611m_mission_t02_v2.0.89.bin, and I am running LwIP on the STM32H563ZIT6 host MCU. I am using the ST67W6X_CLI_LWIP example as a reference to implement a custom TCP stack for my board.Below is my current initialization and Wi-Fi/TCP connection sequence:void network_task(void *argument) { W6X_Status_t ret = 0; W6X_WiFi_Connect_t connectData = {0}; W6X_WiFi_StaStateType_e state = W6X_WIFI_STATE_STA_OFF; wifi_init(); network_log_init(); W6X_App_Cb_t App_cb = {0}; App_cb.APP_wifi_cb = APP_wifi_cb; App_cb.APP_net_cb = NULL; App_cb.APP_ble_cb = NULL; App_cb.APP_mqtt_cb = NULL; App_cb.APP_error_cb = NULL; W6X_RegisterAppCb(&App_cb); app_evt_current = xEventGroupCreate(); /* Initialize the ST67W6X Driver */ ret = W6X_Init(); if (ret != W6X_STATUS_OK) { // TODO: Handle this error appropriately, maybe log it or retry // initialization } vTaskDelay(pdM

Hello,We are experiencing an intermittent CAN-FD issue in our system and would appreciate any advice from the community. We have developed seven new I/O modules based on the STM32G491VETx with an external 20 MHz crystal.All have the same CAN configuration using ISO1042BDWVR. The CANopenNode stack with the CANopenNodeSTM32 driver is implemented on all electronic units.See https://github.com/CANopenNode/CanOpenSTM32  The CAN bus operates at 250 and 500 kbit. All electronic units occasionally experience the problem that the NodeGuarding or heartbeat (set to 3s!!!) stops responding after 24 hours to 5 days. SDOs do not respond either, whilst TPDOs continue to operate. We have set up over 10 networks, each with 4 different nodes (all G491), and all exhibit the same behaviour sporadically. We can rule out hardware faults.The electronic runs for about 48 hours with no Problem on 500k an low bus load (about 2%, Nodeguarding and some TPDO/RPDO).Suddenly FIXFDCAN RF0 FIFO FULL and RX NEW MESSAGE

HI，   I am using stm32wba65i_dk1 board to develop my ble audio application.  I choose zephyr as my software platform and tmap as ble audio profile. However, when the TMAP application initiates advertising, the Pixel 9 cannot detect the device name broadcast by the TMAP peripheral. I also captured over-the-air packets using the professional BLE sniffer X240, which confirmed that no BLE advertising packets were transmitted from the STM32WBA65I_DK1 board.I enabled logging for all HCI commands sent by the HCI Core and all received HCI events, yet no obvious anomalies were observed in the HCI logs. I am unable to identify the root cause of this issue. # 1. LE Set Extended Advertising Parameters [v1]Send Command:[00:00:03.106,000] <dbg> bt_hci_core: bt_hci_cmd_send_sync: buf 0x20010c18 opcode 0x2036 len 25[00:00:03.110,000] <dbg> bt_hci_core: bt_hci_cmd_send_sync: cmd params 00 01 00 20 00 00 30 00 00 07 01 00 00 00 00 00

Hi,STM32H533 datasheet (DS14539 Rev 2) in table 88 says that RDY input setup and hold time are both 0.5ns. From my naive point of view it looks like superb value (RDY have to be stable only +-0.5ns around CLK edge). Isn't that a typo ? (STM32H7 PSSIs hold time is about 5.5ns)Thanks,Michal Dudka

Dear Team,I hope this email finds you well. I am writing to seek your expert clarification on a critical hardware design decision we are currently evaluating for our STM32MP257-based custom board.   --- Current Memory Configuration --- • SoC         : STM32MP257• Memory Part : Micron MT53E1G32D2FW-046 WT:C• Type        : LPDDR4• Density     : 32 Gbit (4 GB)• Organization: 1 x32 (Dual Channel — Channel A + Channel B) --- Our Understanding from ST Documentation --- Based on our research of the following official ST documents: 1. AN5723 (Rev 3, Aug 2024) :   "Interface width is 32-bit when full-populated, or 16-bit when half-populated." 2. AN5724 — DDR Routing Guide:   "For the 16-bit LPDDR4 interface, one 16-bit LPDDR4 is used in point-to-point connection. With this configuration it can drive up to 2 Gbyte memory." 3. AN5489 (Rev 6, Sep 2025) :   STM32MP257 supports both 16-bit (half-populated) and 32-bit (full-populated) LPDDR4 configurations. Our understanding is:• If using a native x1

 I have activated spread spectrum on two of the three PLLs I’m using in an STM32H7S7 via codeLL_PLL_SpreadSpectrumTypeDef sspr2;LL_PLL_SpreadSpectrumTypeDef sspr3;// in SystemClock_Config LL_RCC_PLL2_EnableSpreadSpectrum(); LL_RCC_PLL3_EnableSpreadSpectrum(); sspr2.DitheringRPDFN = 1; sspr2.DitheringTPDFN = 0; sspr2.IncrementStep = 1200; sspr2.ModulationPeriod = 10; sspr2.SpreadMode = LL_RCC_PLL_SPREAD_CENTER; LL_RCC_PLL2_ConfigSpreadSpectrum(&sspr2); sspr3.DitheringRPDFN = 0; sspr3.DitheringTPDFN = 0; sspr3.IncrementStep = 214; sspr3.ModulationPeriod = 60; sspr3.SpreadMode = LL_RCC_PLL_SPREAD_CENTER; LL_RCC_PLL3_ConfigSpreadSpectrum(&sspr3);Is there a way in CubeMX to activate it to make the settings generated automatically, as everything else I’m using?I’ve checked the RCC section in System Core as well as the Clock Configuration tab, but I can’t see anything regarding spread spectrum

Hello everyone,I am facing a flashing/debugging issue with the STEVAL-SPIN3202 Rev 3.1 board.Board:STEVAL-SPIN3202 Rev 3.1Software Used:STM32CubeIDESTM32CubeProgrammerProblem:While trying to flash or debug the board from STM32CubeIDE, I get the following error:"Failed to start GDB server""Error in initializing ST-LINK device""Failed to connect to device"Also, in STM32CubeProgrammer:Read data operation failsTarget connection sometimes not detectedAdditional Observations:ST-LINK USB is detected intermittentlyBoard LED becomes dim/slow ON sometimesReinstalled STM32CubeIDE and driversInstalled ST-LINK driversTried different USB cables and USB portsTried lower SWD frequencyTried Hot Plug modeTried BOOT0 methodStill unable to flash or read targetI would appreciate guidance on:Correct jumper settings for STEVAL-SPIN3202 Rev 3.1Whether onboard ST-LINK firmware may be corruptedPossible hardware protection/reset issueCorrect power supply requirements during flashingThank you.

Hi everyone,Regarding bits [31:16] of the TAFCR register in the STM32H723 RTC, I found that the RM and SVD description files don't match. Could you please tell me if the RM register description or the SVD description file is incorrect?The differences are shown in the following figure: 

We are using the EVSPIN32F06Q1S1 board and have configured TIM1 PWM outputs as CH1/CH1N → PA8/PA7, CH2/CH2N → PA9/PB0, and CH3/CH3N → PA10/PB1. While probing the board, we observed PWM waveforms at test points TP1, TP2, and TP3, which according to the documentation are connected to RES1, RES2, and RES3 rather than to PA8, PA9, and PA10. The complementary outputs are also present and behaving as expected at their respective MCU pins. Could you please clarify how the TIM1 PWM signals are being routed to TP1–TP3 and whether RES1–RES3 are internally connected to the TIM1 outputs on this board?

hello guys i hope you’re doing good,I have a problem while using a Nucleo board STM32F446 with the IHM08M1 driver and a BLDC motor.The issue is that I'm trying to use MATLAB to configure it, and it didn't work. I don't know if the gate driver is necessary to make it work, or maybe the logic (the logic to configure or run the BLDC motor) is not correct. Please, do you have any idea to help us? Can someone tell us how to make it work? i'm really stuck

Hello experts!I’m developing a three-phase motor control application based on the STGIF5CH60TS-L. As suggested by the datasheet I have RC-filters at all low voltage inputs with the required 100ns time constant, in my case it’s 1kOhm and 100pF due to the driving limitation of the MCU’s PWM outputs of 4mA at 3,3V VDD. When I measure the input signals at the IPM, I can see a negative voltage spike for about 100ns which is clamped by an internal diode of the input structure. Naturally, this clamping voltage is around -0,7V and therefore lower than -0,3V given in the absolute maximum ratings. My question is now:Which current magnitude of negative injection can be tolerated by IPM?I could reduce the voltage spike by decrease the resistance in the RC-filter and increase the capacitance simultaneously. That will however require me to use a line driver between the MCU and the IPM, which is no nice solution in my opinion.Best regards!CHEG

Hello,I am designing an NFC reader based on the ST25R300, using the STEVAL-D25R300A schematic as a reference for the antenna matching network. My board uses the same component values on each side of the differential output:L1/L2 = 120 nH (EMC filter series)C11/C8 = 390 pF (EMC filter shunt)C1/C12 = 82 pF each, in parallel (series matching)C14 = 120 pF (shunt)C67 = 39 pF (shunt)C59 = 10 pF, C16 = 150 pF (RFI divider)R3/R4 = 2.2 ohmI could not find the antenna coil parameters in the user manual or the design files. Could you please provide the following for the antenna used on STEVAL-D25R300A?1. Coil inductance at 13.56 MHz2. Coil AC resistance (or Q) at 13.56 MHz3. Whether the antenna is a PCB trace coil or a discrete component, and if it is a PCB trace, the outer dimensions and number of turns4. The target differential impedance the matching network above was designed for Thank you.

Dear ST Support Team,We are currently developing a board based on the ST25DV04K and would appreciate your guidance regarding the antenna interface.In our schematic, we have placed a π coupling filter (series inductors and shunt capacitors) between the AC0/AC1 pins and the antenna matching circuit, upstream of the latter, for coupling at 13.56 MHz, as shown in the attached schematic.Could you please clarify whether the use of this π coupling filter, positioned before the matching circuit, is recommended by ST, or whether it is not necessary in this configuration?Thank you in advance for your support — we look forward to your recommendations.Best regards, 

How tp flash the .elf through CAN , i’m using SPC58EC80E5 and working on Autodevkit studio. 

I’ve designed a flyback w/ Viper27HD.  Turn on voltage is 120Vdc.  Max design input volutage is 500Vdc.  Output voltage is 12V.  I designed the VCC tertiary winding for 16V, but due to spike rectification the actual votlage is 20.2V for Viper VCC.  The prime supply is a MagnaPower SLx-1.5-500-3-xxxxx power supply with voltage, current, power, control and + and - slew rate control. The Viper “wakes up” when the input voltage is at ~110V.  I have an internal POR circuit that holds off my controls until 250 ms later.  When the POR ends, the 12V housekeeping power is used to energize the gate drive of a FET from the input power rail to a large capacitor bank through a 40 Ohm “Soft Start” resistor.  When the gate drive initiates, the Viper chip shuts down for 22 ms which temporarily glitches the housekeeping power.  I’m using a FOD2711 isolation regultor for FB control. I observe: VCC of Viper is STABLE through the shutdown. VBR never approaches the brown out threshold FB switches hard to G

Hello, I wrote a code to erase BANK2 flash memory for STM32G0C1VET6. The thing is that in some cases the erasing part works but in some cases it fails.I wrote the code to be ran in BANK1,the production code will use the proper start address and size, for this testing I’m forcing the erasing to happen in BANK2 for pages 0 and 1. As I commented, in some cases the erasing works, but sometimes there is an error returned by HAL_FLASHEx_Erase, which is HAL_TIMEOUT. I added proper refresh to watchdog and also some PREFETCH calls but even with that the issue persist. Attached is an image of the SR register once the HAL_TIMEOUT is returned. If I continue the execution of the code there is a hard fault caused when calling the HAL_FLASH_Lock (image attached). What could be wrong?I'm using STM32CubeIDE along with Stlink - V3.If the flash is already erased, calling the Erase function could cause the problem?Could it be related to some FLASH latency configurations?bool __attribute__((optimize("O0"))

UART independently working fine but with CAN, it is not working. Even simple welcome msg also no coming over UART . Even when I comment CAN init, issue is there. The error has been conveyed by a member earlier also. Any resolution provided by ST?

This is really a minor one. More an inconvenience than an actual problem. But it would be nice to get it solved, and to gain some understanding of what actually happens.I have a few different applications for various STM32 families, with a homemade bootloader added to it. The bootloaders are placed from address 0x08000000, and the applications begin at a higher address. Typically 0x08010000. The bootloaders and applications run fine. Bootloaders can start the applications, and applications can invoke the bootloaders. No problem there.The only issue I have is when uploading a new application from STM32CubeProgrammer, through the ST-LINK V3. I typically do this when debugging. But when I do it, even if the “Run after programming” checkbox is checked, the microcontroller isn’t started correctly after upload. When I debug this issue, the microcontroller seems to be stuck in an endless loop in the application. (Not the bootloader.)In the code I’m currently working on, this is the place wher

Hi all, I merged the VENC_JPEG_Encoding example with a DCMIPP app. Both parts work on their own, but the JPEG encoding breaks (error -9 = JPEGENC_HW_BUS_ERROR) as soon as I turn on the DCMIPP capture. The JPEG input/output buffer is completely unrelated to the DCMIPP buffer. It’s just that as soon as I start the DCMIPP in CONTINUOUS mode, the JPEG encoder breaks… Very strange.Did anyone else experience this problem? What could cause this? How would I fix this? Best regards, rphii

Hello CommunityThis is my first post here, and I have started learning about the STM32G4xx processors. So I might very well have got something wrong here. I like to ask about a detail in the pin-out picture of the STM32G431 Nucleo64 board in STM32CubeMX software. When I look at the schematics for this Nucleo board, it seems that the PA5 pin can activate the LD2 LED and not the LD1. I guess, that for the typical beginner start blink software, you normally use LD2. When I look at the same picture for the NUCLEO64 STM32G474 board, this PA5 pin activate LD2.The same pin is used for input to an OP-AMP. Would it be possible to use it if you disconnect the SB6 jumper?

I have followed the instructions in GIT  to make ethernet works correctly on STM32H750 (setup TX/RX descriptors and their MPU config, also the LWIP heap and its MPU config, and the RX buffers).Everything seems working correctly after hours of setup and debugging, but the thing that break Ethernet and make it not working is when handling the unicast UDP or the UDP IO stream of OpEner it trigger a BUS Error in MAC DMA and stop everything from working, the explicit communication based on TCP works correctly and doesn’t break the Ethernet.I debugged for days of what could generate a bus fault error, then i find the udp when uses netconn it doesn’t copy the prepared buffer on lwip heap for sendig and in other way it give it directly the address of udp payload from the task stack, and this trigger a Bus Error when calling HAL_ETH_Transmit_IT because the task stack is not DMA accessible.So I made a workarround in low_level_output to detect the payload from outside lwip heap and copy that payl

Hello, I need help configuring the Teseo VIC3DA/VIC3D GPS module.Here’s the background: I’m using the Teseo VIC3D/VIC3DA in one of our current products to replace the module we’re currently using, which has become obsolete (Telit SL869). We cannot modify our software, as it has already been approved by the customer. The idea, therefore, was to use the Teseo VIC3D/VIC3DA as a replacement, which would allow us to keep the LCC-24 enclosure while still being able to configure it before integration and save its configuration to NVM memory.From a hardware perspective, we are not using the dead reckoning feature at this time.We are using the following pins:- PPS (pin 3)- Main UART (pins 20, 21)- VCC_RF, VBATT, VCC (pins 9, 22, 23) connected together to 3.3 [V]- RF_IN (pin 11) with a DC-blocking capacitor because we’re using an active antenna.- All GND pins (pins 10, 12, 13, 24) are connected.Since the following pins are not used on our end, they are left unconnected:- WakeUp (pin 1)- Reserved

Hello:Observation (empirical, multiple boundaries confirmed):When placing DMA linked list nodes (36 bytes each = 9 words) sequentially in SRAM1,if a single node spans certain addresses, the GPDMA channel enters DTEF statewhen fetching that node. Confirmed problematic boundaries in SRAM1 (192KB, 0x20000000 - 0x2002FFFF):- 0x20010000 : crossing FAILS- 0x20020000 : crossing FAILS Both boundaries appear at 64KB intervals within SRAM1, which suggeststhat SRAM1 may be internally organized as multiple 64KB blocks/banks. Test cases:Test 1: Node array starting at 0x20011A54 (natural placement)- Nodes 1-1633: within bank containing 0x20010000-0x2001FFFF → OK- Node 1634: spans 0x2001FFF8 - 0x2002001C → FAILS (crosses 0x20020000) Test 2: Node array starting at (0x20010000 - 44)- The first node spans 0x2000FFD4 - 0x2000FFF8 (OK)- The second node spans 0x2000FFF8 - 0x2001001C → FAILS (crosses 0x20010000) Test 3: Node array starting at (0x20010000 - 36)- The first node ends exactly at 0x20010000- No

Thank you for your replies. Good for me to know, that this marking should have been LD2. I wondered that, I may had got something else wrong about this. It seems to me, that CubeMX assumes, that the SB6 jumper is installed, so you cannot use CubeMX to set the PA5 as input for OPAMP2. But I guess, that you can use some HAL function to do it. Am I right?   CubeMx doesn’t care if SB6 is soldered or not. So remove SB6 and configure PA5 for OPAMP function either in CubeMx or using directly the HAL. When I look the PIN-out view, PA5 is marked red. When I look the reference manual about OPAMPS:Then it seems possible to have OPAM2 use PA5. In CubeMX I look at OPMP2 mode pull down menu, you got “Standalone Internally connected_IO”. But it is marked red and cannot be selected.Post split from this thread for a newer question.