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Error downloading crdb.zipI have tried on both STM32CubeMX 6.18.0 and STM32CubeIde 18.1. Attempting on MacOS(Intel)Tried changing proxy server type to “Use System Proxy Server” Tried different networks. Tried removing cache directories. Tried deleting crdb.zip Previous posts mention downloading (http://xsel.stmcufinder.com/refresh/v2/crdb.zip) manually - appears to be a server issue?Any help appreciated… thanks 

Dear STM Engineer, thank You very much for Your great effort  for the new STM32V8. My comments on the features after looking into stm32v8-presentation.pdf: - STM32V8 will have a ETH-Gb-MAC with PTP, that is great news for applications in the field of scientific instrumentation. -- I am missing PTP-Timestamp-capture-peripherals to generate PTP-precise timestamp input-pulse captures on external events. So triggered by one GPIO input-pulse-edges  (or better several logic-combined GPIOs, at least two to have one "gating), a timestamp (64 Bit or more?) should be stored, including in its timestamp-word at least two (better four or more) GPIO Input-states: state high/low AND edge falling/rising. We would need as many as possible of these PTP-Timestamp-capture-peripherals as possible, e.x. 16 or more of them per MC. Would You consider to include such PTP-Timestamp-capture-peripherals into STM32V8? - -  I am missing PTP-output-pulse-peripherals to generate PTP

 In STM32H7 MCU FW, i am implementing the GPDMA transfer to XSPI in indirect mode, updating DR Register from FW with DMA. I have a custom x8 SPI DDR Slave as target. The issue is i am getting Data transfer error during the HAL_DMA_Transmit_IT function. I have refered the app note for GPDMA - AN5593 where it is mentioned as -  on page 38. I am using SW based trigger to dma since there is no GPDMA req signal for xspi for STM32H7. I want to knowhow to implement software-based trigger if gpdma req signal is not present. I have mentioned the code below. IF there is any workaround to fix the HW DMA req signal issue from xspi? If not then on what other STM device having min of 2 - x8 spi support proper GPDMA transfer with HW DMA req implementation. Code used in my application is mentioned below - static void MX_GPDMA1_XSPI2_TX_Init(void){    __HAL_RCC_GPDMA1_CLK_ENABLE();     hdma_xspi2_tx.Instance = GPDMA1_Channel0;   // use typed instance macro     hdma_xspi2_tx.Init.Request               =

Hello,We are designing a custom board using the STM32MP157FAC1 and have used the STPMIC1APQR PMIC to power the microprocessor, similar to the STM32MP157F-DK2 evaluation board.We need to provide a Power LED on the front panel of the card to indicate that all the power rails generated by the STPMIC1APQR are operating correctly.Since the STPMIC1APQR does not provide a dedicated Power_Good (PGOOD) output signal, we are considering using the RSTn pin (Pin 1) to drive the Power LED along with its connection with NRST pin of STM32MP157FAC1. Our understanding is that RSTn is released (driven high) only after the power-up sequence has completed successfully and all required power rails are within specification. If any monitored power rail fails, RSTn would be asserted low.We plan to use a transistor stage to drive the LED from the **RSTn** signal so that:(1.) RSTn = High: Power LED ON(2.) RSTn = Low: Power LED OFFCould you please confirm whether this is approach is okay or not ? If not, kindly

Figure 14 - Operating modes transition diagram - does not show it: and neither does Table 16 - Operating modes transition criteria: The description of the “reset mechanism” doesn’t really relate to the above state diagram or table: 

Hello ST Community, I noticed that when using the benchmarking tool, datasets larger than 250 MB are automatically reduced using a "representative sampling strategy" that preserves the diversity and distribution of the original data. I would like to understand more details about this process: 1. What specific sampling algorithm/strategy is used? (e.g., random sampling,    stratified sampling, systematic sampling, etc.) 2. How is the target size of 250 MB determined? Is this configurable? 3. How does the tool ensure that the sampled dataset preserves:   - The original data distribution?   - The diversity of data samples?   - Edge cases and boundary values? 4. After optimization, when we validate the model on the full dataset, what    performance differences should we typically expect between the sampled    dataset and the full dataset? 5. Is there any documentation that describes this sampling mechanism in detail? Any information or pointers to relevant documentation would be greatly ap

how can we go initial stm32N6?

Using on a STM32H563RI with trustzone for a secure bootloader and non-secure application. Both the secure and non-secure side were correctly working in OPEN state, and I did a test of going to a CLOSED state and regression back to OPEN with authenticated debug. After the regression, RTC_EnterInitMode(), times out trying to enter init mode and HAL_RTC_Init() fails. I tried the solution from this form post of calling HAL_PWR_EnableBkUpAccess() and that did not work.Notes:- Trustzone and the secure watermarks for the bootloader were reprogrammed in the option bytes after regression.- RTC is LSI as its clock source.- The call to HAL_RCCEx_PeriphCLKConfig() in HAL_RTC_MspInit() returns HAL_OK.- The RTC pheripheral is marked non-secure.- The code has not been changed since preforming the regression and was working previously. The RTC Init Code and Clock configs are included below.void MX_RTC_Init(void) { /* USER CODE BEGIN RTC_Init 0 */ /* USER CODE END RTC_Init 0 */

Setup:I have a CubeMX/CubeIDE-generated STM32G474RET6 project (ThreadX) that I build as a static archive rather than a flashable executable, meant to be linked into a separate top-level consumer application. The consumer supplies main(), calls into this library's init function, and never defines its own vector table, interrupt handlers, or MSP callbacks — this library owns all of that. Problem:A static archive only pulls in the .o members something already-linked actually references (need-driven extraction). That interacts badly with two CubeMX-generated weak-symbol patterns: Vector table vs. stm32g4xx_it.c: startup_stm32g474retx.s gives every handler a .weak/.thumb_set XXX,Default_Handler fallback, satisfied locally from the always-linked startup object. Since nothing else references handlers like NMI_Handler or a peripheral's IRQHandler, the linker never has a reason to pull stm32g4xx_it.c.o out of the archive — the real handlers in it are silently dropped in favor of Default_Handler

I am using an LPS22DF over I2C with an STM32WB5MMG. The sensor is configured for continuous 1 Hz operation, AVG = 64, LPF1 = ODR/4, and continuous dynamic-stream FIFO mode. FIFO samples are retrieved as separate three-byte reads from registers 0x78–0x7A.The first FIFO read after every watermark interrupt is consistently corrupted by approximately +32 hPa. For example, the first value may be raw 4130956 (1008.534 hPa), while the following values are approximately raw 3999700 (976.49 hPa) and agree closely with the standard PRESS_OUT registers. The difference is close to 131072 counts, corresponding to bit 17 of the 24-bit pressure value. This occurs repeatedly for every FIFO batch, not only during startup or LPF settling.  Our operational workaround is to set the FIFO watermark to 11, read eleven three-byte data sets individually, discard the first result, and average the remaining ten. Is this first-read corruption a known LPS22DF behavior or erratum? Is there a required FIFO read sequ

Hi,Using the STM32G431 in PGA mode vs in standalone mode (external resistor network for Gain), I am getting different noise levels on the final output (measured using ADC).The noise generated in PGA mode is twice as big as in standalone mode. What could be the reason?I expect a change in gain due to the tolerance specified in the datasheet, but did not expect the noise level to increase. Note - I tested with multiple combinations for external gain (100R and 1k5, 1k and 15k, 10k and 150k) to reach 16 gain. All the three resulted in similar noise level. Hence, thermal noise could not be the reason is what I assume, in case of PGA. Is some other effect taking presedence here? 

Hello ST Community,I am designing a custom high-power motor controller for an industrial servo motor (RMCS2082) and need advice on component selection, thermal limits, and layout architecture.System Specifications:- Nominal Current: 18.7 A (Continuous load)- Peak / Stall Current: 130 A (Transient spike)- Battery Operating Voltage: 24 Volts- Target Enclosure/Board Temperature: Strictly under 50°C to 60°C Max- Control Method: 20 kHz PWM (generated via external MCU)The Dilemma & My Analysis:I evaluated the VNHD7008AY using TwisterSIM. Brief transient simulations show safe temperatures around 45°C. However, calculating steady-state thermal dissipation for an 18.7A continuous load across the integrated H-bridge path (approx 16-24 mΩ hot) results in 6W to 8W+ of pure heat generation. In a standard PCB design, this localized thermal load will quickly cause a massive temperature rise exceeding my 60°C target and trigger thermal shutdown. Furthermore, the 130A motor stall current exceeds th

After upgrading MX to 6.18.0 when I run STM32CubIDE 1.19 it crashes when doing it’s upgrade check.As it happens so fast I can’t actually see what is happening but managed to open the Preferences to set the Firmware Updater to Off Line Mode..I am using 1.19 as I prefer the MX integration in CubeIDE. So be warned ;)  

Hi ST Community,I'm using an external precision voltage reference connected to the VREF+ pin of the STM32G474.I would like to know:What is the minimum output current capability required for the external VREF source? Is there any specification for the average or peak current drawn from the VREF+ pin during ADC conversions? Does the required current depend on the ADC sampling rate, the number of ADCs operating simultaneously, or the sampling time? I couldn't find a clear specification for the VREF+ input current in the datasheet or reference manual.Any explanation or recommendation would be greatly appreciated.Thank you!

I am using the STM32F051C8T6 MCU for TIG welding project, but PWM is not being generated on my custom TIG control board. Can anyone help me so  

Connected an USB microphone to an H743 as host and it streams mic audio perfectly at 48 KHz for around 5 seconds then the data freezes.SOF is still being called as is AudioHost_IsoDataReadyISR() from the STM IRQ driver, DMA is running (its set to use DMA, I tried without but same behaviour), but the same 96 bytes are transfered every uS: I can clear the receive buffer but it gets refilled with the same data.  Attempts to re-init the pipes etc etc fail to restore streaming.Also, any pause in the servicing of the call to AudioHost_IsoDataReadyISR() results in exactly the same repeat data arriving.This is my own code based on STM’s examples, as I said it runs perfectly for many seconds, if I unplug the microphone it runs again when plugged back in for the same good few seconds.Is there an approved way to restore audio streaming without a full reset when there is an occasional timing glitch in servicing the AudioHost_IsoDataReadyISR() call?

I have an STM32WBA data logging project loosely based on the BLE heart rate project. I sync the RTC via either a BLE message, or NTP from a serial modem. All good; works well and the RTC timestamp ticks along whilst the code is in stop2 sleep. The device is battery-powered, so power is always present. I initialise the RTC in RTC_BINARY_ONLY mode.I track whether the device has received a time sync by stashing a value in one the the backup registers.When the device is reset by a button on the reset line, the RTC gets set to zero. This is not a problem.However, when the device resets by calling NVIC_SystemReset(), the RTC appears to be 4194304 seconds ahead of where it should be. This is 4096 x 1024 seconds. I set the RTC frequency to 1024, so I'm guessing this is something to do with it? My code can handle this after a reset by setting the RTC back by 4096x1024 seconds.What is a more tricky problem is that if the device has been in stop2 mode, and is then woken and reset by&nbs

Hello,I’m using the ADC with DMA for my application where I read the values from a Pot. The DMA is configured to generate interrupts when the DMA buffer is half full and completely full. The readings obtained seem to be correct apart from the fact that there seems to be random 0’s in the buffer. I’m not sure why this happens. Below are the relevant portions of my code: vInit() { /* USER CODE BEGIN ADC1_Init 0 */ /* USER CODE END ADC1_Init 0 */ LL_ADC_InitTypeDef ADC_InitStruct = {0}; LL_ADC_REG_InitTypeDef ADC_REG_InitStruct = {0}; LL_ADC_CommonInitTypeDef ADC_CommonInitStruct = {0}; LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; LL_RCC_SetADCClockSource(SPEED_CONTROL_POT_ADC_CLOCK_SOURCE); /* Peripheral clock enable */ LL_AHB2_GRP1_EnableClock(SPEED_CONTROL_POT_ADC_PERIPH_CLOCK); LL_AHB2_GRP1_EnableClock(SPEED_CONTROL_POT_GPIO_PERIPH_CLOCK); /**ADC1 GPIO Configuration PA0 ------> ADC1_IN1 */ GPIO_InitStruct.

Hi; this question is pretty much the same as another version of it I find on the forums, but it was never answered, so I would like to try asking again.  I’m working through a design that will use an stm32u595 for motor control, and the STSPIN233 as my driver. I will be using three current sense amplifiers on my low-side shunt resistors; each of these need a bias voltage to offset the shunt resistor voltages.  For past prototypes, I worked with an stm32F4, which doesn’t have this nifty VREF+ pin or VREFBUF capability - so I simply used VDDA to create a bias voltage, and used it for my ADC. VDDA itself was drawn from VDD through a ferrite PI filter. I suppose all of this is sort of “lo-fi”, but it worked - I was able to get a motor to turn using FOC.  The stm32u5 is considerably more complex by comparison, so I’ve been trying to teach myself what VREF+/VREFBUF is, and why I might want to use it. Claude, infuriatingly, vacillates from thread to thread in its advice - sometimes it says “O

Hi Everyone,after enabling RTC for the STM32L432KC in STM32CubeMX (version 6.18.0) RTC_WKUP_IRQn doesn't show up in the CubeMX NVIC panel for this MCU but is present in the vector table.Is that a bug or am I missing something?Best regardsGolfBravoRTC configurationMissing RTC wake-up timer interrupt through EXTI line 20? 

Hello community,I am currently working on an STM32F777 project where I encounter a race condition between two DMA-triggered SPI transfers originating from the same timer (TIM8).Setup: MCU: STM32F777 Mechanism 1 (Input Capture): TIM8 CH1 is configured for Input Capture. Upon an active edge, a DMA request transfers a 14-bit data packet to SPI->DR. Mechanism 2 (Periodic Update): TIM8_UP (Update Event) triggers a chained DMA transfer that writes 2 consecutive packets to SPI->DR. The Problem:When both events (TIM8 CH1 Input Capture and TIM8_UP) trigger simultaneously, a collision occurs on the SPI bus: Only 2 packets appear on the SPI MOSI line instead of the expected sequence. The transmitted sequence consists of the packet from the CH1 Capture event followed directly by the second packet of the TIM8_UP chained DMA transfer. The first packet of the TIM8_UP DMA transfer is lost/overwritten. Following this race condition, the entire transfer mechanism halts, and no further pa

Hello,I need to speed up a image processing pipeline and want to offload image scaling to NeoChrom. It should be possible on STM32N6, however:I need nema_core.h and nema_graphics.h. I’ve downloaded TouchGFX via CubeMX, but I don’t see those files anywhere. I think, I need a /port/hardware config/ for STM32N6, but I don’t see any examples in https://github.com/STMicroelectronics/STM32CubeN6/tree/main/Projects/STM32N6570-DKHow should I proceed in this situation?

I’m working with the NUCLEO-WL33CC2 development board and running ST’s CLI demonstration firmware. My goal is to retrieve raw baseband I/Q samples, but I can’t get any I/Q output using the demonstrator commands, specifically IQDump.  If you’ve successfully extracted I/Q from this board using the stock CLI demo, I’d love to know the exact command sequence and any quirks you ran into. Suggestions welcome on required modes, baud rates, or additional steps I might be missing.

  Hello ST Team, I developed a custom USB DFU HOST class on an STM32F446ZE. I soldered a USB-C cable directly to the D+/D-, 5V and GND pins. The Problem: The stack works correctly for transfers up to 128 bytes. However, when I set phost->Control.setup.b.wLength.w > 128 (e.g., 192 bytes) and call USBH_CtlReq, the code enters an infinite loop inside USB_WritePacket. I have traced the execution line-by-line, monitoring the HCTSIZ register values: size (Transfer Size) and cnt (Packet Count). Below is the detailed trace comparing a working 128-byte transfer vs. a failing 192-byte transfer. 1. Successful Scenario: Transferring 128 Bytes Initial State: size = 128, cnt = 2. Loop Iteration 1: i=15: USBx_DFIFO written. Register updates: size = 64, cnt = 2. i=31: USBx_DFIFO written. Register updates: size = 64, cnt = 1. Loop Iteration 2: Initial State: size = 128, cnt = 2. i=15: USBx_DFIFO written. Register updates: size = 64, cnt = 1. i=31: USBx_DFIFO written. Re

Dear Sir,I have using STSPIN32G0A2 to drive a BLDC motor with the 6-step algo. When I use the debugger to reset the board while the motor is spining, the REG12 regulator will be burned out. Pressing reset button (NRST pin) has not killed the board with the running motor and the motor has stopped while pressing reset button. Debugger reset has not killed the board without the motor connection. Debugger reset has pulled low the GPIO (such as) PA15 to pull low the standby pin of the GATE Driver and stop the pin driver the gate of the MOSFET. Debugger reset made the REG12 regulator death while the motor is spinning.I appreciate if you can give me any suggestion. Regards,