STM32N657 RMII Ethernet — RX sampling phase latched wrong at MAC reset (reproducible in PHY loopback)

[jordydehoon.heraeus]

Hi,

  We're hitting intermittent Ethernet RX corruption on the STM32N657 in RMII mode with a LAN8742 PHY. On some cold
  boots the receive path is broken for the whole session: the MAC flags incoming frames with the dribble bit
  (RDES3.DE) and error summary (ES), or drops them entirely, and the MMC alignment-error counter climbs while the
  CRC-error counter stays at zero. TX is fine. It never recovers on its own, and how severe it is varies from board
  to board. It's not tied to auto-negotiation, link state or speed — it's set the moment the MAC comes out of reset.

  The key point: we can reproduce it with the PHY in internal digital loopback, so there's no cable and no link
  partner involved. Frames leave the MAC on the RMII TX pins, loop back inside the PHY, and come back on the RMII RX
  pins. Since it still corrupts there, the problem is in the MAC↔PHY RMII digital interface and the shared 50 MHz
  REF_CLK, not in the cable/magnetics/analog side.

  What fixes it is a MAC-only reset (RCC ETH1 force-reset + reconfigure) while leaving the PHY completely untouched.
  Each reset lands on what looks like a random sampling phase some good, some bad. On this boot it took 4 MAC
  re-inits before we hit a clean phase. A PHY reset on its own never changes anything. So it really looks like the
  EQOS RMII adapter latches its RX di-bit/nibble sampling phase relative to the free-running REF_CLK when it leaves
  reset, and sometimes latches it misaligned.

  We dumped the full MAC/MTL/DMA register set in both the failing and the working state and they're byte-for-byte
  identical (e.g. MACCR=0x0080E403, DMACRXCR=0x00200C01 in both) only clear-on-read status/counters differ. Same
  configuration, opposite behaviour. A corrupted receive descriptor reads RDES3=0x30098044 (FD+LD+DE+ES) even though
  the payload bytes are actually correct; a clean one reads RDES3=0x30010044 (no DE/ES).

  Details: STM32N657X0, IDCODE 0x10006486 (REV_ID 0x1000), MAC version MACVR=0x2052, RMII selected via
  RCC_CCIPR2.ETH1SEL=4, REF_CLK is an external 50 MHz on PF7. We checked ES0620 (device errata rev 4) and there's
  nothing matching in the ETH section.

 

  A few questions:
  - Is it known that the STM32N6 EQOS RMII adapter latches its RX/TX sampling phase relative to the external REF_CLK
  non-deterministically at MAC reset, and can land misaligned?
  - Is there a supported way to force or verify the correct RMII sampling phase at init, instead of resetting the MAC
  until a self-test passes?
  - What are the RMII REF_CLK/RXD setup-hold and MAC↔PHY skew requirements at the MAC pins, so we can review board
  timing on the units where the bad phase actually corrupts data?
  - Is REV_ID 0x1000 affected, and is it fixed in a later revision?

  Thanks


Full log: 

********************************************************************
EthBist: ==== boot self-test (PHY loopback) ====
EthBist: ---- register dump [boot] (for ST support) ----
EthBist: ID   IDCODE=0x10006486 (DEV=0x486 REV=0x1000) MACVR=0x00002052
EthBist: HWF  HWF0R=0x4E0D73F7 HWF1R=0x11141965 HWF2R=0x42041041 HWF3R=0x0C330031
EthBist: CLK  CCIPR2=0x00040000 (ETH1SEL=4) MACPHYCSR=0x00000000
EthBist: MAC  MACCR=0x00800403 MACECR=0x00000600 MACPFR=0x00000404 MACWTR=0x00000000 MACMDIOAR=0x001E0504
EthBist: MAC  MACRXQCR=0x00000000 MACRXQC0R=0x00000002 MACISR=0x00040000 MACRXTXSR=0x00000000 MACDR=0x00000000
EthBist: MTL  MTLOMR=0x00000000 MTLISR=0x00000000 TXQOMR=0x0007000A RXQOMR=0x00700020 TXQUR=0x00000000 RXQMPOCR=0x00000000 TXQDR=0x00000000 RXQDR=0x00000000
EthBist: DMA  DMAMR=0x00000000 DMASBMR=0x01011000 DMADSR=0x00006300
EthBist: DMA0 CCR=0x00000000 TXCR=0x00200001 RXCR=0x00200C01 SR=0x00000004 IER=0x00008041 MFCR=0x00000000
EthBist: DMA0 curTXD=0x24284340 curRXD=0x242843C0 curTXB=0x00000000 curRXB=0x24281340
EthBist: MMC  rxCrcErr=0 rxAlignErr=0 rxUniGood=0 txGood=0
EthBist: PHY  00:0x1000 01:0x7809 02:0x0007 03:0xC131
EthBist: PHY  04:0x01E1 05:0x0001 06:0x0064 07:0x2001
EthBist: PHY  08:0x0000 09:0xFFFF 10:0xFFFF 11:0xFFFF
EthBist: PHY  12:0xFFFF 13:0x0000 14:0x0000 15:0x0000
EthBist: PHY  16:0x0041 17:0x0002 18:0x60E0 19:0xFFFF
EthBist: PHY  20:0x0000 21:0x0000 22:0x0000 23:0x0000
EthBist: PHY  24:0x9B9D 25:0x0000 26:0x0000 27:0x0010
EthBist: PHY  28:0x0000 29:0x0090 30:0x0050 31:0x0040
EthBist: ---- end register dump [boot] ----
EthBist: loopback engaged: BMCR=0x6100 BMSR=0x780D MACCR=0x0080E403
EthBist: frame 0 len=64: rdes3=0x30098044 pl=68 de=1 match=1
EthBist: frame 1 len=64: RX TIMEOUT
EthBist: frame 2 len=64: RX TIMEOUT
EthBist: frame 3 len=256: RX TIMEOUT
EthBist: totals: sent=4 txDone=4 rxOk=0 rxDe=1 rxErr=0 mismatch=0 rxTimeout=3 mmcCrcErr=+0 mmcAlignErr=+4
EthBist: verdict: RMII-LATCHED (frames lost or corrupted this boot)
EthBist: ---- register dump [LATCHED] (for ST support) ----
EthBist: ID   IDCODE=0x10006486 (DEV=0x486 REV=0x1000) MACVR=0x00002052
EthBist: HWF  HWF0R=0x4E0D73F7 HWF1R=0x11141965 HWF2R=0x42041041 HWF3R=0x0C330031
EthBist: CLK  CCIPR2=0x00040000 (ETH1SEL=4) MACPHYCSR=0x00000000
EthBist: MAC  MACCR=0x0080E403 MACECR=0x00000600 MACPFR=0x00000404 MACWTR=0x00000000 MACMDIOAR=0x00000504
EthBist: MAC  MACRXQCR=0x00000000 MACRXQC0R=0x00000002 MACISR=0x00040000 MACRXTXSR=0x00000000 MACDR=0x00000000
EthBist: MTL  MTLOMR=0x00000000 MTLISR=0x00000000 TXQOMR=0x0007000A RXQOMR=0x00700020 TXQUR=0x00000000 RXQMPOCR=0x00000000 TXQDR=0x00000000 RXQDR=0x00000000
EthBist: DMA  DMAMR=0x00000000 DMASBMR=0x01011000 DMADSR=0x00006300
EthBist: DMA0 CCR=0x00000000 TXCR=0x00200001 RXCR=0x00200C01 SR=0x00000506 IER=0x00008041 MFCR=0x00000000
EthBist: DMA0 curTXD=0x24284340 curRXD=0x242843C0 curTXB=0x00000000 curRXB=0x24281340
EthBist: MMC  rxCrcErr=0 rxAlignErr=0 rxUniGood=0 txGood=0
EthBist: PHY  00:0x1000 01:0x7809 02:0x0007 03:0xC131
EthBist: PHY  04:0x01E1 05:0x0001 06:0x0064 07:0x2001
EthBist: PHY  08:0x0000 09:0xFFFF 10:0xFFFF 11:0xFFFF
EthBist: PHY  12:0xFFFF 13:0x0000 14:0x0000 15:0x0000
EthBist: PHY  16:0x0041 17:0x0002 18:0x60E0 19:0xFFFF
EthBist: PHY  20:0x0000 21:0x0000 22:0x0000 23:0x0000
EthBist: PHY  24:0x9B9D 25:0x0000 26:0x0001 27:0x0000
EthBist: PHY  28:0x3000 29:0x0090 30:0x0050 31:0x0040
EthBist: ---- end register dump [LATCHED] ----
EthBist: re-rolling the MAC sampling phase (re-init 1)
EthBist: loopback engaged: BMCR=0x6100 BMSR=0x780D MACCR=0x0080E403
EthBist: frame 0 len=64: rdes3=0x30098044 pl=68 de=1 match=1
EthBist: frame 1 len=64: RX TIMEOUT
EthBist: frame 2 len=64: RX TIMEOUT
EthBist: frame 3 len=256: RX TIMEOUT
EthBist: totals: sent=4 txDone=4 rxOk=0 rxDe=1 rxErr=0 mismatch=0 rxTimeout=3 mmcCrcErr=+0 mmcAlignErr=+4
EthBist: verdict: RMII-LATCHED (frames lost or corrupted this boot)
EthBist: re-rolling the MAC sampling phase (re-init 2)
EthBist: loopback engaged: BMCR=0x6100 BMSR=0x7809 MACCR=0x0080E403
EthBist: frame 0 len=64: RX TIMEOUT
EthBist: frame 1 len=64: RX TIMEOUT
EthBist: frame 2 len=64: RX TIMEOUT
EthBist: totals: sent=3 txDone=3 rxOk=0 rxDe=0 rxErr=0 mismatch=0 rxTimeout=3 mmcCrcErr=+0 mmcAlignErr=+3
EthBist: verdict: RMII-LATCHED (frames lost or corrupted this boot)
EthBist: re-rolling the MAC sampling phase (re-init 3)
EthBist: loopback engaged: BMCR=0x6100 BMSR=0x7809 MACCR=0x0080E403
EthBist: frame 0 len=64: rdes3=0x30098044 pl=68 de=1 match=1
EthBist: frame 1 len=64: rdes3=0x30098044 pl=68 de=1 match=1
EthBist: frame 2 len=64: RX TIMEOUT
EthBist: frame 3 len=256: RX TIMEOUT
EthBist: frame 4 len=256: RX TIMEOUT
EthBist: totals: sent=5 txDone=5 rxOk=0 rxDe=2 rxErr=0 mismatch=0 rxTimeout=3 mmcCrcErr=+0 mmcAlignErr=+5
EthBist: verdict: RMII-LATCHED (frames lost or corrupted this boot)
EthBist: re-rolling the MAC sampling phase (re-init 4)
EthBist: loopback engaged: BMCR=0x6100 BMSR=0x7809 MACCR=0x0080E403
EthBist: frame 0 len=64: rdes3=0x30010044 pl=68 de=0 match=1
EthBist: frame 1 len=64: rdes3=0x30010044 pl=68 de=0 match=1
EthBist: frame 2 len=64: rdes3=0x30010044 pl=68 de=0 match=1
EthBist: frame 3 len=256: rdes3=0x30010104 pl=260 de=0 match=1
EthBist: frame 4 len=256: rdes3=0x30010104 pl=260 de=0 match=1
EthBist: frame 5 len=256: rdes3=0x30010104 pl=260 de=0 match=1
EthBist: frame 6 len=1024: rdes3=0x30010404 pl=1028 de=0 match=1
EthBist: frame 7 len=1024: rdes3=0x30010404 pl=1028 de=0 match=1
EthBist: frame 0 len=1024: rdes3=0x30010404 pl=1028 de=0 match=1
EthBist: totals: sent=9 txDone=9 rxOk=9 rxDe=0 rxErr=0 mismatch=0 rxTimeout=0 mmcCrcErr=+0 mmcAlignErr=+0
EthBist: verdict: CLEAN
EthBist: aligned phase reached after 4 re-roll(s)
EthBist: ---- register dump [CLEAN] (for ST support) ----
EthBist: ID   IDCODE=0x10006486 (DEV=0x486 REV=0x1000) MACVR=0x00002052
EthBist: HWF  HWF0R=0x4E0D73F7 HWF1R=0x11141965 HWF2R=0x42041041 HWF3R=0x0C330031
EthBist: CLK  CCIPR2=0x00040000 (ETH1SEL=4) MACPHYCSR=0x00000000
EthBist: MAC  MACCR=0x0080E403 MACECR=0x00000600 MACPFR=0x00000404 MACWTR=0x00000000 MACMDIOAR=0x00000504
EthBist: MAC  MACRXQCR=0x00000000 MACRXQC0R=0x00000002 MACISR=0x00040000 MACRXTXSR=0x00000000 MACDR=0x00000000
EthBist: MTL  MTLOMR=0x00000000 MTLISR=0x00000000 TXQOMR=0x0007000A RXQOMR=0x00700020 TXQUR=0x00000000 RXQMPOCR=0x00000000 TXQDR=0x00000000 RXQDR=0x00000000
EthBist: DMA  DMAMR=0x00000000 DMASBMR=0x01011000 DMADSR=0x00006300
EthBist: DMA0 CCR=0x00000000 TXCR=0x00200001 RXCR=0x00200C01 SR=0x00000506 IER=0x00008041 MFCR=0x00000000
EthBist: DMA0 curTXD=0x24284340 curRXD=0x242843C0 curTXB=0x00000000 curRXB=0x24281340
EthBist: MMC  rxCrcErr=0 rxAlignErr=0 rxUniGood=0 txGood=0
EthBist: PHY  00:0x1000 01:0x7809 02:0x0007 03:0xC131
EthBist: PHY  04:0x01E1 05:0x0001 06:0x0064 07:0x2001
EthBist: PHY  08:0x0000 09:0xFFFF 10:0xFFFF 11:0xFFFF
EthBist: PHY  12:0xFFFF 13:0x0000 14:0x0000 15:0x0000
EthBist: PHY  16:0x0041 17:0x0002 18:0x60E0 19:0xFFFF
EthBist: PHY  20:0x0000 21:0x0000 22:0x0000 23:0x0000
EthBist: PHY  24:0x9B9D 25:0x0000 26:0x0004 27:0x0000
EthBist: PHY  28:0x0000 29:0x0090 30:0x0050 31:0x0040
EthBist: ---- end register dump [CLEAN] ----
EthBist: ==== self-test done ====

[mƎALLEm]

Hello ​@jordydehoon.heraeus and welcome to the ST community,

Did you check the product errata sheet/Section ETH?

 

[jordydehoon.heraeus]

  Yes, we went through ES0620 Rev 4, Section 2.17 (ETH). The six ETH errata there cover the DMA transfer-state bits
  on a bus error (2.17.1), frame-preemption/FPE status reporting (2.17.2–2.17.3), PTP 802.1AS SYNC identification
  (2.17.4), VLAN tag-filter queue routing (2.17.5), and TSN gate-control-list switching (2.17.6). None of them match
  what we're seeing, and none of those features are even enabled here — we run a plain single-queue RMII setup with
  no FPE, PTP, VLAN filtering or TSN.

  Our symptom is different: the RMII receive sampling phase seems to be latched at MAC reset and occasionally lands
  misaligned, producing RDES3.DE/ES and MMC alignment errors (CRC errors stay at zero), and it reproduces in PHY
  internal digital loopback with no cable or link partner. There's nothing in the ETH errata section describing this.

  So the real question is whether this is a known but undocumented limitation of the N6 EQOS RMII adapter, and
  whether there's a supported way to get a deterministic RMII sampling phase at init instead of resetting the MAC
  until a self-test passes. I'm happy to share the full boot self-test log (a bad boot and a good boot) if that would
  help.

  Thanks
 

[mƎALLEm]

OK,

I forwarded your case internally over this ticket (not accessible by you): CDM0064341

Hope I get an answer.