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I have a requirement from customer to read the mains input voltage (down converted to 3.3V) which is 50Hz using ADC and identify the phase delay between the input and after the ADC reading(Ideally it shall be 0 requirement). How to demonstrate? I am using STM32G474RET6. Please guide. Edit: I am trying to trigger ADC sample at every 20KHz PWM signal.
I am encountering a memory access issue in my application, which runs on Azure RTOS on a custom STM32F767VIT6?based target board. The application receives JPEG images from an MQTT broker via the EC200U modem, using USART on the board. The problem arises when I declare a global array of size 180 KB to store the image. Even though I initialize this array with valid non?zero content (JPEG image data in hex), the debugger consistently shows all zeros when I attempt to read it. Interestingly, when I reduce the array size to 100 KB, the behavior is normal the data is correctly written and read. I am using the ST?Link 2.0 debugger from STMicroelectronics, and the project is built in STM32CubeIDE. Since my JPEG images can be as large as 180 KB, I need to resolve this memory limitation. Could you provide detailed guidance on the root cause of this issue and possible solutions? I have attached my workspace in .7z format for reference.
This account only shares restored community content posted by members between May 22 and June 9, 2026, who did not register for the new community.Hello.I am creating a motor control project for the EVSPIN32G4 using MotorControl Workbench 6.4.1.The EVSPIN32G4 board definition provides configurations for "ThreeShunt_RawCurrents_SingleEnded_ExternalGain" and "ThreeShunt_RawCurrents_SingleEnded_InternalGain," but the current sensing section in the circuit diagram of this board appears to match the "ThreeShunt_RawCurrents_Differential_ExternalGain" configuration.However, adding this configuration causes MotorControl Workbench to fail with an error. This is likely because the definition for "ThreeShunt_RawCurrents_Differential_ExternalGain" does not exist for the STSPIN32G4 in "MC_SDK_6.4.1UtilitiesPC_SoftwareSTMCWBassetsConnectionParameters.json".1. Why is it that the EVSPIN32G4 schematic shows a differential configuration, but the board definition only provides a single-ended option?2. Is
Hi, I am using two STM23F303 Discovery Borads. My application is as follows: The two boards communicate via SPI. Every two seconds the master boards send a uint8 message to the slave. Upon receiving the message, the slave board shall light up some LEDs depending on the sent message. This is a snippet of the code flashed to the slave board:while (FOREVER) { // When you receive a message from if (HAL_SPI_Receive(&hspi1, &u8SpiMsg, U16_NUM_BYTES, HAL_MAX_DELAY) == HAL_OK) { // Set/Reset corresponding LED pins via their control bits in BSRR register GPIOE->BSRR = ...........; } } This is the configuration of the SPI: Mode - Full-Duplex Master/Slave Hardware NSS Signal - Hardware NSS Input Signal Frame Format - Motorola Data Size - 8 bit First Bit - MSB First Prescaler (for Baud Rate) - 8 Clock Polarity - low Clock Phase - 1 Edge CRC Calculation - disable NSSP Mode - Disable The application works, but when I hooked up a logic analyser (saleae logic to inspect
This account only shares restored community content posted by members between May 22 and June 9, 2026, who did not register for the new community.For the VNF9Q20F, the datasheet states that the exposed thermal pad (TAB) is VCC.Can someone confirm that the large exposed pad on the bottom of the package is electrically connected to VBAT/VCC and not GND?If so, should the thermal pad and all thermal vias underneath it be connected to the VBAT copper plane?
This account only shares restored community content posted by members between May 22 and June 9, 2026, who did not register for the new community.We are designing a 6-layer PCB with limited board area. The layer stackup is as follows: TOP / GND2 / SIGNAL / POWER / GND5 / BOTTOM.Due to space constraints, we are planning to place one STPM33 on the TOP side of the board, and another STPM33 rotated 90 degrees directly on the opposite BOTTOM side. Similarly, one STPM34 will be placed on the TOP side, with another STPM34 rotated 90 degrees directly beneath it on the BOTTOM side.In summary, the board will carry a total of four ICs: one STPM33 and one STPM34 on the TOP side, and one STPM33 and one STPM34 on the BOTTOM side, with each TOP-side IC having its counterpart placed directly behind it on the BOTTOM side.Please find attached a diagram illustrating the top/bottom placement of the STPM34. Key points of this layout are as follows:The power supply pin traces on the TOP and BOTTOM sides are
I am currently using the distribution version: V5?rt 6.1.82-rt patch?stm32mp257 I am using the TSN mode of the STM32MP257 switch and found that once I set the date, it reverts to the time before the setting after a period of time, and also causes a probabilistic hang during shutdown or reboot. After investigation,this is caused by the deptp service being enabled in the TSN service. My current application only uses the switch mode and does not require TSN. Is it appropriate to disable deptp? What other services can be disabled to enhance system stability?
This account only shares restored community content posted by members between May 22 and June 9, 2026, who did not register for the new community.I've followed the build instructions for the STM32MP distribution package 6.6.116 and managed to build the boot sd card for MP135F-DK and that works fine.When i build for MP257F-EV1 board, the build works fine and the boot sd card appears ok, but during boot it looks like the kernel load resets the processor partway through : [ 4.201246] m_can_platform 402f0000.can: m_can device registered (irq=76, version=32)[ 4.204152] stm32-cryp 42030000.crypto: will run requests pump with realtime priority[ 4.204774] stm32-pcie 48400000.pcie: IB MEM 0x0080000000..0x00ffffffff -> 0x0080000000[ 4.221546] stm32-pcie 48400000.pcie: iATU: unroll T, 4 ob, 4 ib, align 64K, limit 4G[ 4.255481] stm32-cryp 42030000.crypto: Initialized[ 4.262966] Galcore version 6.4.21.1.1058597NOTICE: CPU: STM32MP257FAI Rev.YNOTICE: Model: STMicroelectronics STM32MP257F-EV1 Eval
HiOne of a small production batch of our boards built around STM32F767ZGT6 has some bizarre behavior. When we tried to program it with STM32CubeProgrammer and a ST-LINK/V2 tool, occasionally we can download a test firmware, but if we power cycle the board, more often than not, we would not be able to download the same firmware again nor to perform a full chip erase. Please see the log below:21:17:34 : Disconnected from device.21:17:35 : UR connection mode is defined with the HWrst reset mode21:17:35 : ST-LINK SN : 53FF6E06498055573337128721:17:35 : ST-LINK FW : V2J45S721:17:35 : Board: --21:17:35 : Voltage: 3.20V21:17:35 : SWD freq: 4000 KHz21:17:35 : Connect mode: Under Reset21:17:35 : Reset mode: Hardware reset21:17:35 : Device ID: 0x45121:17:35 : Revision ID: Rev Z21:17:35 : Debug in Low Power mode is not supported for this device.21:17:36 : UPLOADING OPTION BYTES DATA ...21:17:36 : Bank: 0x0021:17:36 : Address: 0x40023c1421:17:36 : Size: 8 Bytes21:17:36 : UPLOADING ...21:17:36 : Si
This account only shares restored community content posted by members between May 22 and June 9, 2026, who did not register for the new community.Hi,We are currently developing board using the STM32F765 microcontroller and eMMC memory (part numbers: MX52LM08A11XVI and IS21ES08GA-JCLI) via the SDMMC interface in STM32Cube.Can you help us determine if the MX52LM08A11XVI and IS21ES08GA-JCLI can interface with the STM32F765 using the SDMMC peripheral? Thank you
Greetings! I need STHVUP64 detailed datasheet with pinouts. How can I get it?
This account only shares restored community content posted by members between May 22 and June 9, 2026, who did not register for the new community.Hello Team,We are using Qulacomm board QCS8550 Aikri kit with LE r90 release for production, In that there is SSC driver support of LSM6DSV Our setup includes two LSM6DSVTR IMU sensors, and we are attempting to read and write sensor data over SSC using an I2C interface. The I2C bus has been configured in the JSON configuration file for the LSM6DSVTR. Use Case Requirements:Configuring both IMU sensors using the SSC driver with an I2C-based interface Using interrupt pins for data-ready signaling Specifically:INT2 must support an external pulse: Current Status:In the current driver implementation located at:source/adsp_proc/ssc_drivers/lsm6dsv From the driver code analysis, we observed that data is currently being received using a FIFO-based mechanism.Additionally, it appears that the default driver implementation supports only the INT1 interrup
I am debugging my program on a NUCLEO-H533RE and it fails at: { uvalRAM.RAMROM[i] [x] = uvalFla.FlaROM[Page] [x];} which is moving a byte from flash to RAM. The dissembler shows it stopped at 08000d2c: b.n 0x8000d2c Break at address "0x8000d2c" with no debug information available, or outside of program code. Any suggestions on what happened? Compiled and debugged using STM32CubeIDE 2.0.0. I am new to STM32CubeIDE but not new to embedded designs.
This account only shares restored community content posted by members between May 22 and June 9, 2026, who did not register for the new community.[PN]:NUCLEO G071RBX-NUCLEO-IHM08M1Own Motor (4mR, 250uH, 1200rpm, 30Apk, 5pp, inertia known, friction guessed)[VERSION]: Version of MCSDK 6.4.2, STM32 FW 1.6.3[TOOL]: CubeMX 6.17.0, Motor Control Workbench Version: 6.4.2 Build: 260313.082202[DETAILS]:Settings: 20kHz, 100us regulator (2PWM), ADC Sampling 7.5adcclk (234ns), Sensing config see attached.After startup, fails with "Speed Feedback". Plotted graphs show good BEMF response, proper angle and reasonable speed signals (see graphs attached), angle of PLL are somewhat behind OpenLoop. Arround start-up exit speed of 432rpm, the calculated speed of the PLL rises quickly while currents are being reduced, shortly after motor stops.The set target speed in the Motor Pilot is 510 rpm. I tried to switch off UART interface to check if it is linked to MCU load, no success. Debug says "bemfConsistent
Hi, I am using an STM32F767ZI which is connected to a server via Ethernet. It is also connected to other STM32F767ZI devices that are part of the same system, and these devices communicate with each other over CAN. So far, everything is working correctly: the STM32F767ZI with Ethernet communicates with the server using TCP/IP and forwards the information to the other devices connected to the CAN bus. The problem is that I am now being asked to support firmware updates for all the devices connected to the CAN network, including the STM32F767ZI that has the Ethernet connection. I am not sure what the most optimal way to do this would be. I have also never programmed a bootloader before, although I think I should be able to do it. Is there a way to program all the STM32 devices connected to the CAN bus from a server that is connected to the system via an Ethernet cable? Should I change the design so that all devices are connected via Ethernet using TCP/IP and remove the CAN network altoge
Hello, I am working with this guide:How to integrate TouchGFX and camera middleware on an STM32N6570-DK And was wondering if there was an easy way to capture snapshots instead of running the camera continuously. I tried setting the mode to CMW_MODE_SNAPSHOT with no luck. I was able to get snapshot mode to work in the DCMIPP_SnapshotDecimationMode example, but it seems that example interacts with the ISP a little differently from the link above. The end goal is to store snapshots in different locations on PSRAM (multiple cameras muxed to the MCU's CSI port)
Hi everyone, I have a N6 Discovery Kit with a camera. Additionally, I have an N6 Nucleo Board. Now I want to use the CubeMX and CubeIDE to capture a frame on the Nucleo with the camera. I copied most of the things from the `DCMIPP_ContinuousMode` example but I still can't get it working... The I2C communication works (over I2C2) CAM_NRST => GPIO O5 get set to high. CAM_EN => GPIO A0 get set to high. Then I successfully call the IMX335_Probe(..) And finally, it fails here: https://github.com/rphii/NUCLEO_N6_DCMIPP_MB1854B/blob/main/Appli/Core/Src/main.c#L137 (contains the full, minimal, reproducible code) I never get into the `HAL_DCMIPP_PIPE_FrameEventCallback`... If anyone has more experience with the DCMIPP and CSI-2 (which is both new to me) and could help, it'd be greatly appreciated, thanks!
Does anyone know if this part is "Rohs" or "Non-Rohs" compliant? Does anyone have the MDS document (Lead composition)? I wasn't able to find this info on this website.
STM32CubeIDE Version: 2.1.1 Build: 28236_20260312_0043 (UTC) How can I make sense of this ? TMicroelectronics ST-LINK GDB server. Version 7.13.0 Copyright (c) 2026, STMicroelectronics. All rights reserved. Starting server with the following options: Persistent Mode : Disabled Logging Level : 1 Listen Port Number : 61234 Status Refresh Delay : 15s Verbose Mode : Disabled SWD Debug : Enabled Waiting for debugger connection... Debugger connected Waiting for debugger connection... Debugger connected Waiting for debugger connection... ------------------------------------------------------------------- STM32CubeProgrammer v2.22.0 ------------------------------------------------------------------- Log output file: /tmp/STM32CubeProgrammer_Xj0e11.log Error: Unable to connect to the target device, Access port is not valid. Encountered Error when opening /home/soham/st/stm32cubeide_2.1.1/plugins/com.st.stm32cube.ide.mcu.externaltools.cubeprogrammer.linux64_2.2.400.2026010
Hello, We are using STM32F469 and STM32F412 in our design. Regarding the BOOT0 pin, we understand that a pull-down resistor is required to ensure boot from Flash. However, we could not find a clearly specified resistor value in the datasheet or application notes. In many reference designs, a 10k ohm resistor is used. In some cases, lower values such as 510 ohm are used. Could you please clarify the design criteria for selecting the BOOT0 pull-down resistor value? Is there a recommended range? What factors should be considered, for example noise or leakage current? Why are lower values such as 510 ohm sometimes used? We would like to have a clear technical justification for our design. Thank you. Hiroshi Yamada
I just downloaded the installer for 2.22.0 for MacOS on Apple Silicon and the installed program is the Intel version. Thanks
I have a project that builds two different programs with conditional compilation. (I'll call the project Foo and the programs FooA and FooB) I currently have a #define in main.h that I comment/uncomment manually to toggle between them, but I'd like to hoist that into the build system. I could probably manage it with presets, but it looks like I'd have to manually define FooADebug, FooARelease, FooBDebug & FooBRelease, which would be tedious. (If someone does know of a way to make orthogonal sets of presets, I'd be interested) A more promising approach would seem to be something along the lines of:project(Foo) add_executable(FooA) add_executable(FooB) target_compile_definitions(FooB PRIVATE FOO_B) I can see how I would do this if I was writing all the CMakeLists.txt's myself, however while the top CML says# # This file is generated only once, # and is not re-generated if converter is called multiple times. # # User is free to modify the file as much as necessary # cmake/stm32cu
Hi, I want to use my F072's DACs to output a sin and cos signal. to save on memory I want to have only one buffer holding the values of a SIN function, COS values should be taken from the same buffer. Basically, I need the DMA for channel 1 to start from the beginning of the buffer and for channel 2 to start at an offset. Of course, I can't just do something like HAL_DAC_Start_DMA(&hdac1, DAC_CHANNEL_1, lut, no_samples, DAC_ALIGN_12B_R);HAL_DAC_Start_DMA(&hdac1, DAC_CHANNEL_2, lut + no_amples / 4, no_samples, DAC_ALIGN_12B_R);because that would make the dma access elements outside the buffer. in the reference manual I found the register DMA_CNDTRx register, is this the way to go?
HelloI am building Linux on a custom board using the STM32MP255F-AK.The following error occurs during kernel boot:[ 15.371350] stm32-dwmac 482c0000.eth1: Failed to reset the DMA[ 15.386447] stm32-dwmac 482c0000.eth1 end0: stmmac_hw_setup: DMA engine initialization failed[ 15.389570] stm32-dwmac 482c0000.eth1 end0: __stmmac_open: Hw setup failedAfter embedding printk in the kernel source code to investigate,I found that dwmac4_dma_reset() in /drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c was returning ETIMEDOUT(110).[dwmac4_lib.c]int dwmac4_dma_reset(void __iomem *ioaddr) {u32 value = readl(ioaddr + DMA_BUS_MODE);/* DMA SW reset */value |= DMA_BUS_MODE_SFT_RESET;writel(value, ioaddr + DMA_BUS_MODE);return readl_poll_timeout(ioaddr + DMA_BUS_MODE, value,!(value & DMA_BUS_MODE_SFT_RESET),10000, 1000000); }I expect 0x482c0000 to be stored in ioaddr, but different values such as 0x82108000, 0x82128000, and 0x82xxx000 were stored there each time.Ive looked into it from various angles
When I specify a workspace in CubeIDE's File > Switch Workspace, the files appear in the Project Explorer, but they don't match the actual directory. The workspace specified in the IDE is C:WorksSTM32Example_SelectorBLE_HeartRateNUCLEO-WBA25CE1 but it seems to actually be referencing C:WorksSTM32CubeIDEHelloWorld For example, if I modify Srcmain.c in the IDE, it actually updates C:WorksSTM32CubeIDEHelloWorldSrcmain.c Why does this happen? I don't understand what a workspace is.
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