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Hello,I dug deeper into PSSI behavior, and and I observed unwanted behavior. From my point of view it is a bug.PSSI is configured as:OUTEN = 1 (transmit mode)CKPOL = 0 (outputs driven on rising edge, inputs sampled on falling edge)RDYPOL = 0 (0 at input indicates that the receiver is ready to receive)DEPOL = 0 (0 at output indicates that data is valid)DERDYCFG = 0b11 (Both PSSI_RDY and PSSI_DE alternate functions enabled)EDM = 0b00 (Interface captures 8-bit data on every parallel data clock)Chip STM32H7R3Z8T6, clocked at 600MHz from HSI, placed at PCB, powered by 3.3VPSSI kernel clocked by 150MHz and 300MHz (PLL from HSI)Transmitted data is rising numbers from 0 to 15, stored in array in AHBSRAM1, manualy written by core to PSSI->DR as 32bit values (four data bytes at one write). See source code:while (1){ if(PSSI->SR & PSSI_SR_RTT4B){ // wait until space in PSSI buffer PSSI->DR = arr[idxx]; // place data to buffer idxx++; // index to next data if(idxx >= BLOCK_SIZE
IntroWhen I'm using the "STM32CubeIDE for Visual Studio Code" extension, I often want to edit C source files outside of my workspace, which are listed in my CMakeLists.txt and get compiled into the firmware just like any other C file. Unfortunately, with the default setup, the language server (clangd) cannot find some of the headers I include, and it doesn't know the right compilation options, so intelligent features like inlay hints (red squiqqlies) and the "Go to definition" command do not work properly. The ST extension attempts to communicate this kind of information to the language server by putting a ".clangd" file at the root of my workspace folder which has a line in it like "CompilationDatabase: build_release". But clangd won't consider that file when looking at source files outside of the workspace.MotivationI have multiple STM32 projects that share some common libraries, so my folder structure looks like:lib/lib1/lib1.clib/lib1/lib1.hlib/lib2/lib2.clib
Hello,I designed a custom PCB using the STM32F401RE (LQFP64), but I cannot connect to the MCU through SWD. I am using an ST-Link probe and the st-probe command-line tool.When I run the probe command, the ST-Link probe itself is detected, but the target MCU is not properly identified. The tool reports the flash size as 0x00.MCU: STM32F401REDebugger: ST-Link probeTool: st-probeObserved behavior:ST-Link probe is detected correctly.The MCU is not detected.Flash size reported as 0x00.Power measurements:VDD = 3.3 VVDDA = 3.3 V (through ferrite bead BLM18AG601SN1D)VCAP ≈ 1.2 V (2.2 µF capacitor connected directly, ~8 mm trace, no vias)NRST = 3.3 VTotal board current ≈ 18 mA (two LEDs also present)The MCU does not heat up, and current consumption appears normal.Power architecture:12 V input → buck converter → 5 V → LDO → 3.3 V (MCU supply)Analog supply filtering:VDD → ferrite bead → VDDADecoupling capacitors are placed near the MCU.Debug connections:SWDIO → PA13SWCLK → PA14NRST connected to th
I started learning embedded systems recently, and have been using the Nucleo-F303RE board with the STM32CubeIDE toolchain. Recently, I compiled a program and started stepping through it in the debugger. Everything worked fine as always. I started to modify a single line of code, but decided not to make any changes as I wanted to run the debugger again first. Despite being the exact same program, it took much longer to reach the breakpoint in main from the startup ... maybe 10 seconds instead of 1.5 seconds. Single stepping through a line or a single instruction worked, but was clearly must slower than before. Stepping over a function that writes maybe 10 registers took about 10 seconds. When I let the program run freely, it was no longer reaching a breakpoint in my SysTick handler, even though it was before. How can I get the debugger to work?I tried cleaning the project and rebuilding, but that didn't work. I tried another simple program to make sure the board or ST_Link wasn't someho
I'm getting the "elf has a LOAD segment with RWX permissions" warning, and a quick search here reveals a couple of ways to get around this: Disable the warning, or edit the .ld file.However, in my case, I'm using the upper half of the STM32's flash area to emulate non-volatile memory. So I want my flash to be writeable.Can anyone suggest some magic to put in my linker file that will make the warning go away, but also allow me to write to flash?Also: I'm using STM32CubeIDE, so my linker file is auto-generated. Is there a user-override mechanism (like there is in the source code)?Thanks.
Title edited to state the issue being discussed.Really? After all these years? Padawan
Hi, I am seeking some guidance.With the new release STM32CubeIDE for Visual Studio Code 3.8.0, it says it comes with new features including " Serial terminal: Enabling developers to easily setup serial communication for example leveraging the ST-LINK virtual com port."In the docs, there is not much explanation on how to get this working. I only see:"If the serverPort attribute is defined, two ports are used by the ST-LINK GDB server: one for the debug session and serverPort + 1 for the SWO connection.These ports are reserved even if SWO is not activated in the debug configuration."How would one activate the SWO in the launch.json? I went through all the options with completition and none seem to activate or configure the SWO.I know that with the extension "Cortex-Debug" provided by marus25 we could configure the SWO as so:"swoConfig": { "enabled": true, "cpuFrequency": 275000000, // must match -a (Hz) :contentReference[oaicite:4]{index=4} "swoFrequency"
Hi, I'm trying to measure X-Nucleo-nfc03a1 with VNA: i got completely different values for C11 C22 and C2 as is on nucleo board. I understood something wrong? and when I remove Resistors 330ohm, inductor and 4 100pF capacitors I got like:
We are developing a STiROT/OEMuROT bootloader for a customer using the above chip. This is based on the STM32H7S78-DK sample. The customer has developed the main application and have added support to download a new firmware image over Ethernet. This image is stored in external RAM and once downloaded an md5 checksum of the image is stored and a flag is set to indicate that new firmware is available. At this point the device is restarted to switch to the bootloader. We've added code to the bootloader that checks if a new firmware image is available in external RAM. If a new image is available the bootloader validates that the image is OK by recalculating the md5 checksum. The validation passes and at this point a section in external FLASH is erased. After the erase completes, the image in external RAM is copied into the external FLASH and the copied image is validated via md5 checksum - which fails. On further investigation it is the data being read from external RAM that is incorrect (
In OEMiROT_Boot/Src/low_level_ext_flash.c, function Ext_Flash_EraseSector(), a call is made to EXTMEM_MemoryMappedMode() immediately before the sector erase takes place, to temporarily disable memory-mapped mode for the external flash, with the function called again afterwards to re-enable it.As @ken5 reported previously, we found that these flash erases can cause corruption in the external RAM.After a lot of experimentation and head-scratching, we've found that if the external RAM is also removed from the memory map before a flash erase, and re-enabled afterwards, these corruption issues appears to go away (pending further testing).I'm guessing that this wasn't spotted in ST's testing because OEMiROT doesn't use the external RAM until later (if at all), so any corruption doesn't matter. However, our adapted OEMiROT does use the external RAM, and the data corruption was a serious problem.(Incidentally, we saw occasional corruption in the external fla
I am using STM32h757xih6 Controller Ethernet pinging data transfer issue came by using lwip and udp protocol getting hard fault handler (polling method)
Hello, I am experiencing a problem with ADC1 and ADC2. I configured them in Dual Regular Simultaneous Mode, where ADC1 acts as the master and ADC2 acts as the slave. The ADC channel connections are as follows: ADC1 Channel 1: 24V_Sense ADC1 Channel 2: 5V_Sense ADC2 Channel 14: IOut_Sense ADC2 Channel Vrefint: Internal reference voltage However, I noticed that IOut_Sense always has a value, while 24V_Sense is unstable and fluctuating. OUTPUT:V24:24011 mV | V5:3 mV | I:23653 mA V24:8807 mV | V5:3 mV | I:8675 mA V24:8726 mV | V5:1 mV | I:8675 mA V24:8844 mV | V5:3 mV | I:8675 mA V24:23767 mV | V5:1 mV | I:23528 mA V24:23853 mV | V5:0 mV | I:23590 mA V24:23727 mV | V5:0 mV | I:23435 mA V24:23968 mV | V5:0 mV | I:23481 mA V24:8832 mV | V5:3 mV | I:8675 mA V24:23541 mV | V5:0 mV | I:23388 mA uint32_t adc_dual_buffer[4]; int main(void) { HAL_Init(); SystemClock_Config(); MX_GPIO_Init(); MX_ADC1_Init(); MX_ADC2_Init(); MX_USART1_UART_Init(); MX_I2C1_Init();
Split from STM32CubeIDE version 2.1.0 won't generate IOC project file as this is a new question.Please keep to one question per thread.Thanks both Ghofrane GSOURI & Andrew Neil for pointers. Adopting the method shown in the presentation. I have selected a nucleo development board to create an STM32MX project. I have then created a STM32CubeIDE projecfrom the MX project. Having not written any code yet, I'm getting compilation errors but have no idea why? The errors are relating to files marked with a red x below:
Please note that the user authentication service will be under maintenance on 12 March at 5:30 AM CET (10:00 AM IST) for approximately one hour. During this period, some disruptions may occur. The impact is limited to versions earlier than STM32CubeMX V6.16 and STM32CubeIDE V2.0.0. The service returns to normal soon after maintenance is complete. What to do if you encounter a problem If you experience issues during the maintenance window, please use st.com or try again after one hour. If the problem persists after that time, contact us through the Community for further assistance. Update 13 March 2026: The maintenance was successfully completed as scheduled on 12 March. If you encounter any issues, please do not hesitate to contact us.
Hi,I powered the NUCLEO-F410RB board externally by changing the JP5 jumper to select the E5V power supply and applied 5 V to the E5V pin. Initially, I did not have an external ST-LINK, so I switched JP5 to U5V and programmed the Nucleo board through USB.During this back-and-forth process, I powered both internally and externally at a time. After this, the board started consuming more current, and U1 in the NUCLEO-F410RB schematic overheated. Eventually, the VOUT and GND pins were found to be shorted. After troubleshooting, I found that the short was inside the on-board debugger IC (ST-LINK), between VDD and VSS, so I removed the debugger IC.Later, I purchased an external ST-LINK and tried to program the Nucleo board again. I powered the board externally with 5 V on E5V. The main MCU is getting 3.3 V, but there is almost no current consumption, whereas earlier it used to draw around 200–700 mA.For debugging, I removed the CN2 jumpers and made the following connections:C
I'm trying to set up FSMC in muxed mode to read_write external NOR flash devices. Muxed pins goes through 2 8-bit latches 74HC574D.The problem is that currently i can barely read from external NOR and it's not accepting commands.Firstly HAL_NOR_Init(&hnor1, &Timing, NULL) returns HALL_ERR since it fails to read CommandSet from NOR. It should read address 0x13 from CFI and get 0x02 or 0x01 as a result, but write commad makes no effect and as a result driver reads at 0x13 from memopry start.After analyzing what's going on on the FSMC bus I still cand fing any clues. Here is an example how it performs ReadID sequence, using standard HAL_NOR_ReadID Everything looks correct, 3 sequences 0x555 - >0xAA, 0x2AA -> 0x55 and 0x555 -> 0x90, but reading 0x00 and 0x01 right after returns data from NOR not the deviceID I've also tried bitbang mode with same pins and code below successfully reads deviceID. So after all it's not a witing problem, but maby timings or so
Hello,When generating a basic Bluetooth project for NUCLEO‑WBA55CG using STM32CubeMx 6.17 (and 6.16) with Cmake as the toolchain, the project compilation fails to a missing symbol during the link stage.Here is the error message:le_ctrl.c:(.text.HCI_READ_LOCAL_VERSION_INFORMATION+0x20): undefined reference to `ll_sys_get_brief_fw_version'After investigation, it turns out the issue is caused by the incorrect order of linked static BLE libraries in the generated CMake file "cmake/stm32cubemx/CMakeLists.txt". CubeMX places the Link Layer and BLE Stack libraries in an order that prevents the linker from resolving symbols correctly. Reordering the libraries fixes the issue.Here is the corrected order that resolves the error:# Project static libraries set(MX_LINK_LIBS :stm32wba_ble_stack_basic.a :WBA5_LinkLayer_BLE_Basic_lib.a STM32_Drivers ${TOOLCHAIN_LINK_LIBRARIES} Utilities STM32_WPAN Common ) Best regards
Hi Together,I am currently trying to use the FMAC hardware accelerator. Normal usage already works. Now for numerical stability I want to implement the filter as second order sections (sos). According to RM0481:Cascaded filters must either be combined into a single stage, or implemented asseparate filters. In the latter case, multiple sets of filter coefficients can be pre-loadedinto the memory, one set per stage, and only the X2_BASE address changed to selectwhich set is used.To do this I currently:Concatenate all the stage coeffs into one vector:static int16_t const b_Coeffs_0[b_Coeff_len_0] = { 55, 111, 55 }; static int16_t const a_Coeffs_0[a_Coeff_len_0] = { -3745, -258 }; static int16_t const b_Coeffs_1[b_Coeff_len_1] = { 16384, 32767, 16384 }; ...static int16_t all_coeffs[sos_Coeff_Count] = { b_Coeffs_0[0], b_Coeffs_0[1], b_Coeffs_0[2], a_Coeffs_0[0], ...On setup input the vector as b coefficients:filter_Config.Clip = FMAC_CLIP_ENABLED; filter_Config.Filter = FMAC_FUNC_IIR_DIRECT
Having some issues trying to debug a FreeRTOS project using JLink, using an STM32U5G9 (Riverdi 5" Display Board) If I enable "serverRtos" in the launch configuration:"configurations": [ { "type": "jlinkgdbtarget", "request": "launch", "name": "STM32Cube: STM32 Launch JLink GDB Server", "origin": "snippet", "cwd": "${workspaceFolder}", "preBuild": "${command:st-stm32-ide-debug-launch.build}", "runEntry": "main", "serverSpeed": "12000", "serverRtos": { "enabled": true, "port": "60000", "driver": "freertos", "driverPort": "ARM_CM33_NTZ" }, "preRunCommands": [ "monitor exec SetRTTSearchRanges 0x200bb800 0x234800" ], "imagesAndSymbols": [ { "imageFileName": "${command:st-stm32-ide-debug-launch.get-projects-binary-from-context1}" } ] } ]And then try to start a debug session, i get a disconnect error:Reading 20 bytes @ address 0x200C2A5C Read 4 bytes @ address 0x200C2A28 (Data = 0x200C2970) Read 4 bytes @ address 0x200C2A58 (Data = 0x200BEA20) Read 4 bytes @ add
Hi team,Can you please help me with the Single Event Effect (SEE) analysis, Type of technology used, Technology Feature Size details for LDCL015MR?
Hello,I want to develop a LoRaWAN sensor with STM32WL5MOCHxS, but I can't activate the LSE and HSE clock in CubeMX.Is there a way to make the adjustments in the .ioc?The configuration is possible in STM32WL5MOCH (expired).
Hello ST,1. ds14258 Rev.6 Table 57 on p.163 specifies a positive I_inj of "N/A" for pins other than PA4, PA5, PB2, PB12,PC14, PC15, PD8, and PH2 (as opposed to a positive I_inj of "0 mA" in the row above for pins PA4, PA5, PB2, PB12, PC14, PC15, PD8, and PH2) Does "N/A" mean that it is *impossible* to cause any positive injection (on pins other than PA4, PA5, PB2, PB12,PC14, PC15, PD8, and PH2) with pin voltages between 0V and 4V when VDD is unpowered or at 0V?i.e. Do pins other than PA4, PA5, PB2, PB12, PC14, PC15, PD8, and PH2 have some kind of "nice" input structure that allows powering them when VDD is unpowered or at 0V? 2. ds14258 Rev.6 states in Note 3 on p.128: "Positive injection (when VIN > VDDIOx) is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value." Does "not possible" in the above sentence mean:a. that externally raising the voltage on those pins to between 0V and 4V when VDD is unpowe
TouchGFX adds a redundant line ending to .cproject file when clicking generate code even if nothing has changed.This causes changes to show up in git and also makes merging and pull requests more complicated.In STM32CubeIDE the line ending is removed after making any change to the project (and optionally reverting the change). -<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> +<?fileVersion 4.0.0?> +<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> I'm using TouchGFX 4.23.2, but the problem was also present in older versions. Using STM32CubeIDE 1.15.1, but older version had the same effect.Please fix this.
The image sensor inputs a 24 MHz clock and outputs a 40 MHz clock, and the captured image size is 1280×1024×2. When the trigger mode of the image sensor is enabled, the main loop execution speed slows down by approximately 1.6 seconds; when the trigger mode is disabled, the system operates normally. Furthermore, I intend to transmit the images collected by DCMI via USB, but these two modules cannot be enabled simultaneously. Additionally, when the DCMI is operating, serial port interrupts will cause abnormal operation of the DCMI. How should I resolve this issue? Below is the configuration code and main loop code of my STM32H743:
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