Hi @Christophe VRIGNAUD ,I am using Eclipse on Linux; the connection is with JLink so it is using JLinkGDBServer on the host side.The SFR view is determined by the SVD file you use. The official SVD has the ECC units like you are showing, but it is m...

@Christophe VRIGNAUD OK, let's do it one more time.The ECC interrupt occurs; scanning the state registers reveals a 1 at address 0x52009044 (single bit failure).This belongs to D1 domain (RAMECC1) monitor 2 (address offset 0x40), which is, according ...

@KORourke Now I know what the "interleaved" means.For DTCM, it's not that the two RAM blocks are put one after another, like it is the case for D2 SRAM.They are interwoven, i.e. we have a 64-bit bus but accessing two 32-bit units of RAM (of 64 kB = 1...

@KORourke Putting together RM0433 table 11 (ECC controller mapping) and table 7 (memory layout),I came to the conclusion that DTCM, SRAM1 and SRAM2 are those meant as "interleaved", which means that despite of looking like continuous RAM they are sub...

@Christophe VRIGNAUD That does not really work out. I got the following notification (on STM32H753AII):RAMECC1_M1SR (0x52009044) = 3 (Single and double ECC error)OK, so this is D1 monitor 2 which belongs to ITCM. Should be a 64-bit bus.RAMECC1_M1FAR ...