Posted on September 20, 2013 at 08:58just precise my answer : concerning data setup and hold times they are hardware coded in a loockup table depending on FREQ value.
Posted on September 20, 2013 at 08:47The timings granularity depends on the APB clock frequency. FREQ is used only for data setup and hold times. CCR is used for all timings related to the master clock. If you refer to STM32F3 reference manual for i...
Posted on September 18, 2013 at 15:23CCR field is used to generate the SCL master clock. FREQ is used by the hardware to generate data setup and hold times respecting the standards whatever APB frequency.
Posted on September 18, 2013 at 08:55If you refer to NXP I2C specifications, you will find that each mode must respect some timings. In the STM32F1/F2/F4/L1 I2C, these timings are hardware coded and depend on the value programmed in FREQ field. If y...
Posted on September 17, 2013 at 17:27I am from ST, working in application team in charge of I2C in MCUs. You are correct and the new I2C peripheral present in STM32F0 and STM32F3 families is designed as you say. In older families, the I2C clock freq...
