We used to have that working but now can only used weak or medium drive on the SPI pins (SCK & SOUT).Pin mapper or manual editing of the board.c file only gives us weak (0) or medium drive(1){(int16_t)MSCR_IO_INDEX(PORT_D, SCK_4), PAL_LOW, (iomode_t)...

We have the SARADC up and running in DMA mode on 1 channel as per the sample application.But when we add 2 more channels we can't get it to go throgh the callback routin. (saradcconfdma_ch1_conf_cb & saradcconfdma_ch2_conf_cb) and hence we don´t get ...

Worked perfect 2 years ago, then after updating the SPC5Studio we can´t get the SARADC to compile without alot of errors in the saradc_lld_cfg.c file (attached picture). We tried to use the old saradc_lld_cfg.c file and we could compile it but the ad...

Using the SPC572Lxx RLA GTM DPLL Test Application for Discovery all works fine until for some reason the Cluster Clocks in the Clock Manager Unit of the GTM IP Configuration changes to what´s shown in the picture and we get the Error "2' is not a val...