I've been trying to build-time reserve a 64KiB memory region anywhere between 0xC0000000 & 0xDFFFFFFF for the Cortex-M4 core using a device tree reserved-memory node. I've tried 0xC0000000, 0xD0000000 & 0xDFFF0000 but each time U-Boot fails either du...
Hi. I'm using the v2.1.0 ecosystem to build for a target that will boot TF-A & U-Boot from a single ISSI IS25LP016D-JNLE 2 mebibyte quad-SPI NOR flash connected with the rest of the system in e.MMC. (This is to work around the bug in the rev.B STM32M...
I'm using the 2.1.0 ecosystem with an STM32MP157A-EV1 and am having some problems with running a customized FreeRTOS build on the M4 core while running Linux on the A7s.I have modifed the linker script so that the code is in SRAM1&SRAM2, resource tab...
I worked out what the problem was a while ago. It turns out that the JTAG debugger attaches after the code has begun to run and may be in an ISR when it takes control. I've added some code to delay enabling interrupts (actually the whole start up) fo...
Me too. All the documentation suggests STGENR is the way to share timestamps between domains yet I've not found any device or sys interface to do so on the Linux A7 side. We're using the M4 core to interface to a bunch of analog & digital I/O devices...
Thanks for the details & pointers @Community member .I'll take a look.FYI:-We're still using ST's ecosystem v2.1.0 (dunfell-5.4) as we have drivers that have not yet been ported to kernel > 5.4. (We plan to move everything up of course but we're sti...
Thanks for the reply Kevin. I had actually looked at those but they don't explain why a "reserved-memory" node at 0xDFFF0000-to 0xDFFFFFFF causes U-Boot to fail claiming that it can't reserve memory for the FDT below 0xD0000000.Nor do they explain wh...
Hi Olivier. Thanks for the reply and the pointers to previous discussion which is very useful.However you've not actually answered my question. Is there any documentation on where I can reserve DDR without U-Boot choking? This would be useful knowled...
