Posted on November 03, 2005 at 15:16Hi Anthony, I was told by ST that the /ss only acts as a gate. This is probably correct since test patterns would occasionally be split across frames. As for SiLabs, they have been around a while (and have full do...
Posted on October 28, 2005 at 15:45We have tried a similar thing with very poor results. The port is not documented and somewhat unreliable (/SS setup times? continuous clocking? FIFO interrupts and others). I would suggest looking for another solut...
Posted on October 06, 2005 at 13:56The difficulty is probably the /ss signal. The master needs to generate a /cs pulse that is active for each transfer (x8 or x16 bit) You cannot use the master /ss signal for this. when the SPI is in master mode, th...
Posted on September 13, 2005 at 11:51see the STR71x USB lib document. It describes callback function non-standared (not impemented in standard lib) requests pg12/16. 2.4.3 Device property The USB core will dispatch the control to user program whenev...
Posted on August 31, 2005 at 10:59USB is bit overwhelming at first. Basically it starts with enumeration where the HOST(pc) sends requests for structures that describe the hw. This is the bit that is overwhelming. Luckily, this is all taken care of ...
