Posted on July 26, 2006 at 04:18There are NO double write cycle on PCI bus if I use PCI 2.0 in North AND South bridge in Vega !!! What is it? I'll read in STPC BIOS Writer's Guide p. 3.4: ''The PCI 2.1 protocol introduced retry cycles, which allow a...
Posted on June 21, 2006 at 03:37I've disabled all write posting feature (clear all bits), but I've see on digital analyzer rare double write cycles (on issue command sequence for flash programm operation). Can somebody to offer another solution this...
Posted on June 07, 2006 at 10:05Yes, I've tested it. All that bits cleared (write posting disable). I need control bits for write posting from Host to PCI, not Host to CPU!
Posted on June 07, 2006 at 05:29I've found in ''STPC VEGA Programming Manual ver. 3.0'' write posting control bits for data transfer from PCI to Host Memory, IDE to Host Memory and ISA to Host Memory. But I did not found write posting control bit fo...
Posted on June 06, 2006 at 05:43I have double write cycle, when i try programm flash memory (AM29DL323�?¡ (AMD)) on PCI bus of the embedded module, based on STPC VEGA processor. It happens seldom (about one time in ~2000 write cycles). The similar s...
