Posted on May 17, 2011 at 15:05Hi,
Frupi,
The HSI is selected as default clock source;)
Regarding the CLK block diagram: the fHSI is divided by the prescaler that can be configured through HSIDIV[1:0] bits in the CLK_CKDIVR register (the reset value for these bit is 1 so, it divide the fHSI/4 by default) for more details refer to reference manual.
When you use the mode output compare PWM1 you don't need to configure the interrupt.
Coluber,
Yes, the timerx(x=1,2,3,4,5) when available on the product (refer to product datasheet) is the same as the described one in the STM8S microcontroller family reference manual.
Regards
mozra
